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Searched refs:IS_GEMINILAKE (Results 1 – 19 of 19) sorted by relevance

/dragonfly/sys/dev/drm/i915/
H A Dintel_cdclk.c1203 WARN(IS_GEMINILAKE(dev_priv), "Unsupported divider\n"); in bxt_get_cdclk()
1273 WARN(IS_GEMINILAKE(dev_priv), "Unsupported divider\n"); in bxt_set_cdclk()
1407 if (IS_GEMINILAKE(dev_priv)) { in bxt_init_cdclk()
1757 else if (IS_GEMINILAKE(dev_priv)) in intel_pixel_rate_to_cdclk()
1798 if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv)) { in intel_crtc_compute_min_cdclk()
1950 if (IS_GEMINILAKE(dev_priv)) { in bxt_modeset_calc_cdclk()
1962 if (IS_GEMINILAKE(dev_priv)) { in bxt_modeset_calc_cdclk()
2021 else if (IS_GEMINILAKE(dev_priv)) in intel_compute_max_dotclk()
2072 } else if (IS_GEMINILAKE(dev_priv)) { in intel_update_max_cdclk()
H A Dintel_dsi.c550 else if (IS_GEMINILAKE(dev_priv)) in intel_dsi_device_ready()
833 if (!IS_GEMINILAKE(dev_priv)) in intel_dsi_pre_enable()
845 if (IS_GEMINILAKE(dev_priv)) { in intel_dsi_pre_enable()
857 if (IS_GEMINILAKE(dev_priv) && !glk_cold_boot) in intel_dsi_pre_enable()
932 else if (IS_GEMINILAKE(dev_priv)) in intel_dsi_clear_device_ready()
1548 if (IS_GEMINILAKE(dev_priv)) { in intel_dsi_prepare()
1586 if (!IS_GEMINILAKE(dev_priv)) { in intel_dsi_unprepare()
H A Dintel_csr.c300 } else if (IS_GEMINILAKE(dev_priv)) { in parse_csr_fw()
455 else if (IS_GEMINILAKE(dev_priv)) in intel_csr_ucode_init()
H A Dintel_atomic.c328 if (IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) { in intel_atomic_setup_scalers()
H A Dintel_device_info.c364 if (IS_GEN10(dev_priv) || IS_GEMINILAKE(dev_priv)) in intel_device_info_runtime_init()
H A Dintel_fbc.c295 if (IS_GEN9(dev_priv) && !IS_GEMINILAKE(dev_priv)) { in gen7_fbc_activate()
901 if (IS_GEN9(dev_priv) && !IS_GEMINILAKE(dev_priv)) in intel_fbc_get_reg_params()
H A Dintel_hdmi.c1232 else if (IS_GEMINILAKE(dev_priv)) in intel_hdmi_source_max_tmds_clock()
1496 if (scdc->scrambling.supported && IS_GEMINILAKE(dev_priv)) { in intel_hdmi_compute_config()
2033 if (IS_GEMINILAKE(dev_priv)) in intel_hdmi_init_connector()
H A Dintel_dsi_pll.c217 if (IS_GEMINILAKE(dev_priv)) { in bxt_dsi_pll_is_enabled()
H A Dintel_dpll_mgr.c1444 if (IS_GEMINILAKE(dev_priv)) { in bxt_ddi_pll_enable()
1532 if (IS_GEMINILAKE(dev_priv)) { in bxt_ddi_pll_enable()
1560 if (IS_GEMINILAKE(dev_priv)) { in bxt_ddi_pll_disable()
H A Dintel_dsi_vbt.c643 mul = IS_GEMINILAKE(dev_priv) ? 8 : 2; in intel_dsi_vbt_init()
H A Dintel_color.c660 } else if (IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) { in intel_color_init()
H A Dintel_dpio_phy.c214 if (IS_GEMINILAKE(dev_priv)) { in bxt_get_phy_list()
H A Dintel_runtime_pm.c688 if (IS_GEMINILAKE(dev_priv)) { in bxt_verify_ddi_phy_power_wells()
2510 } else if (IS_GEMINILAKE(dev_priv)) { in intel_power_domains_init()
H A Dintel_engine_cs.c1459 else if (IS_GEMINILAKE(dev_priv)) in init_workarounds_ring()
H A Dintel_sprite.c266 if (IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) { in skl_update_plane()
H A Di915_drv.h3001 #define IS_GEMINILAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_GEMINILAKE) macro
3089 (IS_GEMINILAKE(dev_priv) && IS_REVID(dev_priv, since, until))
H A Di915_perf.c2759 } else if (IS_GEMINILAKE(dev_priv)) { in i915_perf_register()
H A Dintel_pm.c3968 if (IS_GEMINILAKE(to_i915(intel_crtc->base.dev))) in skl_check_pipe_max_pixel_rate()
4617 if ((IS_BROXTON(dev_priv) || IS_GEMINILAKE(dev_priv)) && in skl_compute_linetime_wm()
9028 else if (IS_GEMINILAKE(dev_priv)) in intel_init_clock_gating_hooks()
H A Dintel_display.c3507 if (!IS_GEMINILAKE(dev_priv) && !IS_CANNONLAKE(dev_priv)) { in skl_plane_ctl()
5409 psl_clkgate_wa = (IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) && in haswell_crtc_enable()
9198 if (IS_GEMINILAKE(dev_priv) || INTEL_GEN(dev_priv) >= 10) { in haswell_get_pipe_config()
12786 if (IS_GEMINILAKE(dev_priv)) in skl_max_scale()