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Searched refs:IS_GEN9_BC (Results 1 – 14 of 14) sorted by relevance

/dragonfly/sys/dev/drm/i915/
H A Dintel_ddi.c629 if (IS_GEN9_BC(dev_priv)) { in intel_ddi_get_buf_trans_edp()
665 if (IS_GEN9_BC(dev_priv)) { in intel_ddi_get_buf_trans_hdmi()
783 } else if (IS_GEN9_BC(dev_priv)) { in intel_ddi_hdmi_level()
841 if (IS_GEN9_BC(dev_priv) && in intel_prepare_dp_ddi_buffers()
875 if (IS_GEN9_BC(dev_priv) && in intel_prepare_hdmi_ddi_buffers()
1495 else if (IS_GEN9_BC(dev_priv)) in intel_ddi_clock_get()
2115 if (IS_GEN9_BC(dev_priv)) in ddi_signal_levels()
2148 } else if (IS_GEN9_BC(dev_priv)) { in intel_ddi_clk_select()
2174 else if (IS_GEN9_BC(dev_priv)) in intel_ddi_clk_disable()
2240 if (IS_GEN9_BC(dev_priv)) in intel_ddi_pre_enable_hdmi()
H A Dintel_i2c.c86 else if (IS_GEN9_BC(dev_priv)) in get_gmbus_pin()
103 else if (IS_GEN9_BC(dev_priv)) in intel_gmbus_is_valid_pin()
H A Dintel_runtime_pm.c602 if (IS_GEN9_BC(dev_priv)) in gen9_enable_dc5()
634 if (IS_GEN9_BC(dev_priv)) in skl_disable_dc6()
2412 if (IS_GEN9_BC(dev_priv) || IS_CANNONLAKE(dev_priv)) { in get_allowed_dc_mask()
2504 } else if (IS_GEN9_BC(dev_priv)) { in intel_power_domains_init()
3001 } else if (IS_GEN9_BC(dev_priv)) { in intel_power_domains_init_hw()
3042 else if (IS_GEN9_BC(dev_priv)) in intel_power_domains_suspend()
H A Dintel_mocs.c181 if (IS_GEN9_BC(dev_priv) || IS_CANNONLAKE(dev_priv)) { in get_mocs_settings()
H A Dintel_cdclk.c2050 } else if (IS_GEN9_BC(dev_priv)) { in intel_update_max_cdclk()
2243 } else if (IS_GEN9_BC(dev_priv)) { in intel_init_cdclk_hooks()
2255 else if (IS_GEN9_BC(dev_priv)) in intel_init_cdclk_hooks()
H A Dintel_color.c656 } else if (IS_BROADWELL(dev_priv) || IS_GEN9_BC(dev_priv) || in intel_color_init()
H A Dintel_audio.c708 if (!IS_GEN9_BC(dev_priv))
H A Dintel_fbc.c543 if (IS_BROADWELL(dev_priv) || IS_GEN9_BC(dev_priv)) in find_compression_threshold()
H A Dintel_pm.c3559 if (IS_GEN9_BC(dev_priv) || IS_BROXTON(dev_priv)) in skl_needs_memory_bw_wa()
6537 IS_GEN9_BC(dev_priv) || IS_CANNONLAKE(dev_priv)) { in gen6_init_rps_frequencies()
6550 if (IS_GEN9_BC(dev_priv) || IS_CANNONLAKE(dev_priv)) { in gen6_init_rps_frequencies()
6873 if (IS_GEN9_BC(dev_priv) || IS_CANNONLAKE(dev_priv)) { in gen6_update_ring_freq()
6891 if (IS_GEN9_BC(dev_priv) || IS_CANNONLAKE(dev_priv)) { in gen6_update_ring_freq()
H A Dintel_dpll_mgr.c2425 else if (IS_GEN9_BC(dev_priv)) in intel_shared_dpll_init()
H A Dintel_dp.c242 } else if (IS_GEN9_BC(dev_priv)) { in intel_dp_set_source_rates()
1819 if (intel_dp_is_edp(intel_dp) && IS_GEN9_BC(dev_priv)) { in intel_dp_compute_config()
H A Di915_drv.h3116 #define IS_GEN9_BC(dev_priv) (IS_GEN9(dev_priv) && !IS_LP(dev_priv)) macro
H A Di915_gem_gtt.c2127 else if (IS_GEN9_BC(dev_priv) || IS_GEN10(dev_priv)) in gtt_write_workarounds()
H A Dintel_display.c9126 else if (IS_GEN9_BC(dev_priv)) in haswell_get_ddi_port_state()
13641 if (found || IS_GEN9_BC(dev_priv)) in intel_setup_outputs()
13657 if (IS_GEN9_BC(dev_priv) && in intel_setup_outputs()