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Searched refs:LANE_COUNT_DP_MAX (Results 1 – 3 of 3) sorted by relevance

/dragonfly/sys/dev/drm/amd/display/dc/
H A Ddc_dp_types.h37 LANE_COUNT_DP_MAX = LANE_COUNT_FOUR enumerator
104 struct dc_lane_settings lane_settings[LANE_COUNT_DP_MAX];
/dragonfly/sys/dev/drm/amd/display/dc/core/
H A Ddc_link_dp.c168 union dpcd_training_lane dpcd_lane[LANE_COUNT_DP_MAX] = { { {0} } }; in dpcd_set_lt_pattern_and_lane_settings()
432 union lane_adjust dpcd_lane_adjust[LANE_COUNT_DP_MAX] = { { {0} } }; in get_lane_status_and_drive_settings()
507 union dpcd_training_lane dpcd_lane[LANE_COUNT_DP_MAX] = {{{0}}}; in dpcd_set_lane_settings()
615 union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX]; in perform_post_lt_adj_req_sequence()
729 union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX] = { { {0} } }; in perform_channel_equalization_sequence()
793 union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX]; in perform_clock_recovery_sequence()
799 for (lane = 0; lane < LANE_COUNT_DP_MAX; lane++) { in perform_clock_recovery_sequence()
2608 unsigned char link_qual_pattern[LANE_COUNT_DP_MAX] = {0}; in dc_link_dp_set_test_pattern()
2716 for (lane = 0; lane < LANE_COUNT_DP_MAX; lane++) in dc_link_dp_set_test_pattern()
/dragonfly/sys/dev/drm/amd/display/include/
H A Dlink_service_types.h73 struct dc_lane_settings lane_settings[LANE_COUNT_DP_MAX];