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Searched refs:LC_LINK_WIDTH_RD_MASK (Results 1 – 9 of 9) sorted by relevance

/dragonfly/sys/dev/drm/radeon/
H A Drv770d.h953 # define LC_LINK_WIDTH_RD_MASK 0x70 macro
H A Dnid.h1102 # define LC_LINK_WIDTH_RD_MASK 0x70 macro
H A Dsid.h1509 # define LC_LINK_WIDTH_RD_MASK 0x70 macro
H A Dcikd.h370 # define LC_LINK_WIDTH_RD_MASK 0x70 macro
H A Drv770.c2054 lanes = (link_width_cntl & LC_LINK_WIDTH_RD_MASK) >> LC_LINK_WIDTH_RD_SHIFT; in rv770_pcie_gen2_enable()
H A Devergreend.h1487 # define LC_LINK_WIDTH_RD_MASK 0x70 macro
H A Dr600d.h904 # define LC_LINK_WIDTH_RD_MASK 0x70 macro
H A Dr600.c4553 lanes = (link_width_cntl & LC_LINK_WIDTH_RD_MASK) >> LC_LINK_WIDTH_RD_SHIFT; in r600_pcie_gen2_enable()
H A Dci_dpm.c4858 link_width = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL) & LC_LINK_WIDTH_RD_MASK; in ci_get_current_pcie_lane_number()