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Searched refs:PHYPLL_PIXEL_RATE_CNTL (Results 1 – 2 of 2) sorted by relevance

/dragonfly/sys/dev/drm/amd/display/dc/dce/
H A Ddce_hwseq.h74 SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 0), \
75 SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 1), \
76 SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 2), \
77 SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 3), \
78 SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 4), \
79 SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 5)
212 uint32_t PHYPLL_PIXEL_RATE_CNTL[6]; member
310 HWS_SF1(blk, PHYPLL_PIXEL_RATE_CNTL, PHYPLL_PIXEL_RATE_SOURCE, mask_sh),\
311 HWS_SF1(blk, PHYPLL_PIXEL_RATE_CNTL, PIXEL_RATE_PLL_SOURCE, mask_sh)
365 HWS_SF1(OTG0_, PHYPLL_PIXEL_RATE_CNTL, PHYPLL_PIXEL_RATE_SOURCE, mask_sh), \
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H A Ddce_hwseq.c177 REG_UPDATE_2(PHYPLL_PIXEL_RATE_CNTL[tg_inst], in dce_crtc_switch_to_clk_src()
191 if (REG(PHYPLL_PIXEL_RATE_CNTL[tg_inst])) in dce_crtc_switch_to_clk_src()
192 REG_UPDATE(PHYPLL_PIXEL_RATE_CNTL[tg_inst], in dce_crtc_switch_to_clk_src()