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Searched refs:RADEON_RING_TYPE_GFX_INDEX (Results 1 – 22 of 22) sorted by relevance

/dragonfly/sys/dev/drm/radeon/
H A Dradeon_asic.c215 [RADEON_RING_TYPE_GFX_INDEX] = &r100_gfx_ring
230 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
232 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
234 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
283 [RADEON_RING_TYPE_GFX_INDEX] = &r100_gfx_ring
300 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
379 [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring
396 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
447 [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring
464 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
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H A Dni.c1479 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false; in cayman_cp_enable()
1491 if (ring->idx == RADEON_RING_TYPE_GFX_INDEX) in cayman_gfx_get_rptr()
1507 if (ring->idx == RADEON_RING_TYPE_GFX_INDEX) in cayman_gfx_get_wptr()
1520 if (ring->idx == RADEON_RING_TYPE_GFX_INDEX) { in cayman_gfx_set_wptr()
1561 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; in cayman_cp_start()
1627 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; in cayman_cp_fini()
1636 RADEON_RING_TYPE_GFX_INDEX, in cayman_cp_resume()
1737 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = true; in cayman_cp_resume()
1741 r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]); in cayman_cp_resume()
1743 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false; in cayman_cp_resume()
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H A Dr420.c207 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; in r420_cp_errata_init()
227 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; in r420_cp_errata_fini()
269 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX); in r420_startup()
H A Drv770.c1078 if (rdev->asic->copy.copy_ring_index == RADEON_RING_TYPE_GFX_INDEX) in r700_cp_stop()
1082 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false; in r700_cp_stop()
1125 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; in r700_cp_fini()
1780 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX); in rv770_startup()
1809 ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; in rv770_startup()
1964 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ring_obj = NULL; in rv770_init()
1965 r600_ring_init(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX], 1024 * 1024); in rv770_init()
H A Dr100.c715 if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) { in r100_irq_set()
779 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX); in r100_irq_process()
890 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; in r100_copy_blit()
952 r = radeon_fence_emit(rdev, &fence, RADEON_RING_TYPE_GFX_INDEX); in r100_copy_blit()
1122 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; in r100_cp_init()
1221 radeon_ring_start(rdev, RADEON_RING_TYPE_GFX_INDEX, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]); in r100_cp_init()
1222 r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, ring); in r100_cp_init()
1249 radeon_ring_fini(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]); in r100_cp_fini()
1257 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false; in r100_cp_disable()
2959 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; in r100_debugfs_cp_ring_info()
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H A Dradeon_ring.c61 case RADEON_RING_TYPE_GFX_INDEX: in radeon_ring_supports_scratch_reg()
517 static int radeon_gfx_index = RADEON_RING_TYPE_GFX_INDEX;
H A Dr200.c89 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; in r200_copy_dma()
122 r = radeon_fence_emit(rdev, &fence, RADEON_RING_TYPE_GFX_INDEX); in r200_copy_dma()
H A Dsi.c3459 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false; in si_cp_enable()
3621 ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; in si_cp_fini()
3654 ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; in si_cp_resume()
3733 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = true; in si_cp_resume()
3736 r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]); in si_cp_resume()
3738 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false; in si_cp_resume()
4747 case RADEON_RING_TYPE_GFX_INDEX: in si_ib_parse()
6372 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX); in si_irq_process()
6384 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX); in si_irq_process()
6694 ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; in si_startup()
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H A Dr600.c2416 if (rdev->asic->copy.copy_ring_index == RADEON_RING_TYPE_GFX_INDEX) in r600_cp_stop()
2420 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false; in r600_cp_stop()
2697 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; in r600_cp_start()
2727 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; in r600_cp_resume()
2777 r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, ring); in r600_cp_resume()
2783 if (rdev->asic->copy.copy_ring_index == RADEON_RING_TYPE_GFX_INDEX) in r600_cp_resume()
2811 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; in r600_cp_fini()
3169 ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; in r600_startup()
3323 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ring_obj = NULL; in r600_init()
4305 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX); in r600_irq_process()
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H A Dradeon_ib.c274 if (i == RADEON_RING_TYPE_GFX_INDEX) { in radeon_ib_ring_tests()
H A Dr520.c189 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX); in r520_startup()
H A Drs600.c674 if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) { in rs600_irq_set()
783 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX); in rs600_irq_process()
996 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX); in rs600_startup()
H A Devergreen.c2981 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; in evergreen_cp_start()
3047 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; in evergreen_cp_resume()
3104 r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, ring); in evergreen_cp_resume()
4504 if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) { in evergreen_irq_set()
4517 if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) { in evergreen_irq_set()
4842 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX); in evergreen_irq_process()
4849 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX); in evergreen_irq_process()
4859 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX); in evergreen_irq_process()
5032 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX); in evergreen_startup()
5061 ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; in evergreen_startup()
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H A Dcik.c3555 case RADEON_RING_TYPE_GFX_INDEX: in cik_hdp_flush_cp_ring_emit()
3911 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false; in cik_cp_gfx_enable()
4108 ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; in cik_cp_gfx_resume()
4140 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = true; in cik_cp_gfx_resume()
4141 r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]); in cik_cp_gfx_resume()
4143 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false; in cik_cp_gfx_resume()
5716 int usepfp = (ring->idx == RADEON_RING_TYPE_GFX_INDEX); in cik_vm_flush()
7905 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX); in cik_irq_process()
7915 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX); in cik_irq_process()
8380 ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; in cik_startup()
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H A Dradeon_cs.c213 p->ring = RADEON_RING_TYPE_GFX_INDEX; in radeon_cs_get_ring()
222 p->ring = RADEON_RING_TYPE_GFX_INDEX; in radeon_cs_get_ring()
H A Drs400.c423 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX); in rs400_startup()
H A Dradeon_fence.c1041 case RADEON_RING_TYPE_GFX_INDEX: return "radeon.gfx"; in radeon_fence_get_timeline_name()
H A Dradeon_kms.c509 *value = rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready; in radeon_info_ioctl()
H A Drs690.c712 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX); in rs690_startup()
H A Dr300.c1404 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX); in r300_startup()
H A Drv515.c533 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX); in rv515_startup()
H A Dradeon.h143 #define RADEON_RING_TYPE_GFX_INDEX 0 macro