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Searched refs:REG_GET (Results 1 – 25 of 32) sorted by relevance

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/dragonfly/sys/dev/drm/amd/display/dc/dcn10/
H A Ddcn10_hubp.c95 REG_GET(DCHUBP_CNTL, in hubp1_get_underflow_status()
812 REG_GET(HUBPRET_CONTROL, in hubp1_read_state()
843 REG_GET(BLANK_OFFSET_1, in hubp1_read_state()
846 REG_GET(DST_DIMENSIONS, in hubp1_read_state()
877 REG_GET(NOM_PARAMETERS_0, in hubp1_read_state()
881 REG_GET(NOM_PARAMETERS_1, in hubp1_read_state()
884 REG_GET(NOM_PARAMETERS_4, in hubp1_read_state()
887 REG_GET(NOM_PARAMETERS_5, in hubp1_read_state()
912 REG_GET(NOM_PARAMETERS_2, in hubp1_read_state()
919 REG_GET(NOM_PARAMETERS_6, in hubp1_read_state()
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H A Ddcn10_mpc.c133 REG_GET(MPCC_TOP_SEL[mpcc_id], MPCC_TOP_SEL, &top_sel); in mpc1_is_mpcc_idle()
134 REG_GET(MPCC_OPP_ID[mpcc_id], MPCC_OPP_ID, &opp_id); in mpc1_is_mpcc_idle()
135 REG_GET(MPCC_STATUS[mpcc_id], MPCC_IDLE, &idle); in mpc1_is_mpcc_idle()
147 REG_GET(MPCC_TOP_SEL[mpcc_id], in mpc1_assert_mpcc_idle_before_connect()
380 REG_GET(MUX[tree->opp_id], MPC_OUT_MUX, &out_mux); in mpc1_init_mpcc_list_from_hw()
384 REG_GET(MPCC_OPP_ID[mpcc_id], MPCC_OPP_ID, &opp_id); in mpc1_init_mpcc_list_from_hw()
385 REG_GET(MPCC_TOP_SEL[mpcc_id], MPCC_TOP_SEL, &top_sel); in mpc1_init_mpcc_list_from_hw()
386 REG_GET(MPCC_BOT_SEL[mpcc_id], MPCC_BOT_SEL, &bot_sel); in mpc1_init_mpcc_list_from_hw()
400 REG_GET(MPCC_OPP_ID[bot_mpcc_id], MPCC_OPP_ID, &opp_id); in mpc1_init_mpcc_list_from_hw()
420 REG_GET(MPCC_OPP_ID[mpcc_inst], MPCC_OPP_ID, &s->opp_id); in mpc1_read_mpcc_state()
[all …]
H A Ddcn10_optc.c699 REG_GET(OTG_V_SYNC_A_CNTL, in optc1_enable_reset_trigger()
1200 REG_GET(OTG_STEREO_STATUS, in optc1_is_stereo_left_eye()
1213 REG_GET(OTG_CONTROL, in optc1_read_otg_state()
1220 REG_GET(OTG_V_SYNC_A_CNTL, in optc1_read_otg_state()
1223 REG_GET(OTG_V_TOTAL, in optc1_read_otg_state()
1226 REG_GET(OTG_V_TOTAL_MAX, in optc1_read_otg_state()
1229 REG_GET(OTG_V_TOTAL_MIN, in optc1_read_otg_state()
1250 REG_GET(OTG_H_SYNC_A_CNTL, in optc1_read_otg_state()
1253 REG_GET(OTG_H_TOTAL, in optc1_read_otg_state()
1272 REG_GET(OTG_CONTROL, in optc1_get_otg_active_size()
[all …]
H A Ddcn10_dpp.c106 REG_GET(CM_IGAM_CONTROL, in dpp_read_state()
108 REG_GET(CM_IGAM_CONTROL, in dpp_read_state()
110 REG_GET(CM_DGAM_CONTROL, in dpp_read_state()
112 REG_GET(CM_RGAM_CONTROL, in dpp_read_state()
114 REG_GET(CM_GAMUT_REMAP_CONTROL, in dpp_read_state()
H A Ddcn10_hw_sequencer.c1513 REG_GET(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, in mmhub_read_vm_system_aperture_settings()
1515 REG_GET(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, in mmhub_read_vm_system_aperture_settings()
1518 REG_GET(MC_VM_SYSTEM_APERTURE_LOW_ADDR, in mmhub_read_vm_system_aperture_settings()
1521 REG_GET(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, in mmhub_read_vm_system_aperture_settings()
1542 REG_GET(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32, in mmhub_read_vm_context0_settings()
1544 REG_GET(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32, in mmhub_read_vm_context0_settings()
1547 REG_GET(VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32, in mmhub_read_vm_context0_settings()
1549 REG_GET(VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32, in mmhub_read_vm_context0_settings()
1552 REG_GET(VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32, in mmhub_read_vm_context0_settings()
1554 REG_GET(VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32, in mmhub_read_vm_context0_settings()
[all …]
H A Ddcn10_dpp_cm.c235 REG_GET(CM_TEST_DEBUG_DATA, in dpp1_cm_program_color_matrix()
490 REG_GET(CM_TEST_DEBUG_DATA, in dpp1_program_input_csc()
667 REG_GET(CM_IGAM_LUT_RW_CONTROL, CM_IGAM_DGAM_CONFIG_STATUS, in dpp1_degamma_ram_inuse()
757 REG_GET(CM_IGAM_LUT_RW_CONTROL, CM_IGAM_DGAM_CONFIG_STATUS, in dpp1_ingamma_ram_inuse()
827 REG_GET(CM_IGAM_CONTROL, CM_IGAM_LUT_MODE, &ram_num); in dpp1_program_input_lut()
H A Ddcn10_link_encoder.c494 REG_GET(DIG_BE_EN_CNTL, DIG_ENABLE, &value); in dcn10_is_dig_enabled()
1263 REG_GET(DP_MSE_SAT_UPDATE, in dcn10_link_encoder_update_mst_stream_allocation_table()
1266 REG_GET(DP_MSE_SAT_UPDATE, in dcn10_link_encoder_update_mst_stream_allocation_table()
1286 REG_GET(DIG_BE_CNTL, DIG_FE_SOURCE_SELECT, &field); in dcn10_link_encoder_connect_dig_be_to_fe()
H A Ddcn10_hubbub.c547 REG_GET(DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL, in hubbub1_toggle_watermark_change_req()
H A Ddcn10_stream_encoder.c780 REG_GET(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, &reg1); in enc1_stream_encoder_dp_blank()
/dragonfly/sys/dev/drm/amd/display/dc/dce/
H A Ddce_abm.c66 REG_GET(BL_PWM_PERIOD_CNTL, BL_PWM_PERIOD, &bl_period); in get_current_backlight_16_bit()
67 REG_GET(BL_PWM_PERIOD_CNTL, BL_PWM_PERIOD_BITCNT, &bl_int_count); in get_current_backlight_16_bit()
70 REG_GET(BL_PWM_CNTL, BL_ACTIVE_INT_FRAC_CNT, (uint32_t *)(&bl_pwm)); in get_current_backlight_16_bit()
71 REG_GET(BL_PWM_CNTL, BL_PWM_FRACTIONAL_EN, &fractional_duty_cycle_en); in get_current_backlight_16_bit()
339 REG_GET(LVTMA_PWRSEQ_REF_DIV, BL_PWM_REF_DIV, in dce_abm_immediate_disable()
353 REG_GET(BL_PWM_CNTL, BL_ACTIVE_INT_FRAC_CNT, &value); in dce_abm_init_backlight()
381 REG_GET(LVTMA_PWRSEQ_REF_DIV, BL_PWM_REF_DIV, in dce_abm_init_backlight()
H A Ddce_mem_input.c588 dmif_buffer_control = REG_GET(DMIF_BUFFER_CONTROL, in dce_mi_allocate_dmif()
625 dmif_buffer_control = REG_GET(DMIF_BUFFER_CONTROL, in dce_mi_free_dmif()
682 REG_GET(GRPH_UPDATE, GRPH_SURFACE_UPDATE_PENDING, &update_pending); in dce_mi_is_flip_pending()
H A Ddce_link_encoder.c549 REG_GET(DIG_BE_EN_CNTL, DIG_ENABLE, &value); in dce110_is_dig_enabled()
1309 REG_GET(DP_MSE_SAT_UPDATE, in dce110_link_encoder_update_mst_stream_allocation_table()
1312 REG_GET(DP_MSE_SAT_UPDATE, in dce110_link_encoder_update_mst_stream_allocation_table()
1332 REG_GET(DIG_BE_CNTL, DIG_FE_SOURCE_SELECT, &field); in dce110_link_encoder_connect_dig_be_to_fe()
H A Ddce_aux.c261 *sw_status = REG_GET(AUX_SW_STATUS, AUX_SW_REPLY_BYTE_COUNT, in read_channel_reply()
277 REG_GET(AUX_SW_DATA, AUX_SW_DATA, &reply_result_32); in read_channel_reply()
294 REG_GET(AUX_SW_DATA, AUX_SW_DATA, &aux_sw_data_val); in read_channel_reply()
H A Ddce_clock_source.c476 REG_GET(PLL_CNTL, PLL_REF_DIV_SRC, &field); in dce110_get_pix_clk_dividers_helper()
648 REG_GET(PIXEL_RATE_CNTL[inst], DP_DTO0_ENABLE, &dto_enabled); in dce110_get_d_to_pixel_rate_in_hz()
653 REG_GET(PHASE[inst], DP_DTO0_PHASE, &phase); in dce110_get_d_to_pixel_rate_in_hz()
654 REG_GET(MODULO[inst], DP_DTO0_MODULO, &modulo); in dce110_get_d_to_pixel_rate_in_hz()
H A Ddce_opp.c438 REG_GET(CONTROL, in program_formatter_420_memory()
H A Ddce_clocks.c184 REG_GET(DPREFCLK_CNTL, DPREFCLK_SRC_SEL, &dprefclk_src_sel); in dce_get_dp_ref_freq_khz()
189 REG_GET(DENTIST_DISPCLK_CNTL, DENTIST_DPREFCLK_WDIVIDER, &dprefclk_wdivider); in dce_get_dp_ref_freq_khz()
H A Ddce_transform.c1156 REG_GET(DCFE_MEM_PWR_STATUS, in program_pwl()
1164 REG_GET(DCFE_MEM_LIGHT_SLEEP_CNTL, in program_pwl()
H A Ddce_dmcu.c275 REG_GET(DMCU_STATUS, UC_IN_RESET, &dmcu_uc_reset); in dce_is_dmcu_initialized()
/dragonfly/sys/dev/drm/amd/display/dc/gpio/
H A Dhw_gpio.c45 REG_GET(MASK_reg, MASK, &gpio->store.mask); in store_registers()
46 REG_GET(A_reg, A, &gpio->store.a); in store_registers()
47 REG_GET(EN_reg, EN, &gpio->store.en); in store_registers()
86 REG_GET(Y_reg, Y, value); in dal_hw_gpio_get_value()
H A Dhw_hpd.c89 REG_GET(int_status, in get_value()
/dragonfly/sys/dev/drm/amd/display/dc/i2caux/dce110/
H A Di2c_hw_engine_dce110.c128 REG_GET(DC_I2C_SW_STATUS, DC_I2C_SW_STATUS, &i2c_sw_status); in release_engine()
194 REG_GET(SPEED, DC_I2C_DDC1_PRESCALE, &pre_scale); in get_speed()
239 REG_GET(DC_I2C_SW_STATUS, DC_I2C_SW_STATUS, &i2c_sw_status); in is_hw_busy()
245 REG_GET(DC_I2C_SW_STATUS, DC_I2C_SW_STATUS, &i2c_sw_status); in is_hw_busy()
407 REG_GET(DC_I2C_DATA, DC_I2C_DATA, &i2c_data); in process_channel_reply()
421 REG_GET(DC_I2C_SW_STATUS, DC_I2C_SW_STATUS, &i2c_sw_status); in get_channel_status()
531 REG_GET(MICROSECOND_TIME_BASE_DIV, XTAL_REF_DIV, &xtal_ref_div); in construct()
H A Daux_engine_dce110.c286 *sw_status = REG_GET(AUX_SW_STATUS, AUX_SW_REPLY_BYTE_COUNT, in read_channel_reply()
302 REG_GET(AUX_SW_DATA, AUX_SW_DATA, &reply_result_32); in read_channel_reply()
319 REG_GET(AUX_SW_DATA, AUX_SW_DATA, &aux_sw_data_val); in read_channel_reply()
/dragonfly/sys/dev/drm/amd/display/dc/bios/
H A Dbios_parser_helper.c61 REG_GET(BIOS_SCRATCH_6, S6_ACC_MODE, &acc_mode); in bios_is_accelerated_mode()
/dragonfly/sys/dev/drm/amd/display/dc/inc/
H A Dreg_helper.h49 #ifdef REG_GET
50 #undef REG_GET
156 #define REG_GET(reg_name, field, val) \ macro
/dragonfly/sys/dev/drm/amd/display/dc/dce100/
H A Ddce100_resource.c398 REG_GET(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO, &straps->dc_pinstraps_audio); in read_dce_straps()

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