Searched refs:SDMA0_REGISTER_OFFSET (Results 1 – 8 of 8) sorted by relevance
/dragonfly/sys/dev/drm/radeon/ |
H A D | cik_sdma.c | 70 reg = SDMA0_GFX_RB_RPTR + SDMA0_REGISTER_OFFSET; in cik_sdma_get_rptr() 94 reg = SDMA0_GFX_RB_WPTR + SDMA0_REGISTER_OFFSET; in cik_sdma_get_wptr() 115 reg = SDMA0_GFX_RB_WPTR + SDMA0_REGISTER_OFFSET; in cik_sdma_set_wptr() 259 reg_offset = SDMA0_REGISTER_OFFSET; in cik_sdma_gfx_stop() 309 reg_offset = SDMA0_REGISTER_OFFSET; in cik_sdma_ctx_switch_enable() 341 reg_offset = SDMA0_REGISTER_OFFSET; in cik_sdma_enable() 374 reg_offset = SDMA0_REGISTER_OFFSET; in cik_sdma_gfx_resume() 482 WREG32(SDMA0_UCODE_ADDR + SDMA0_REGISTER_OFFSET, 0); in cik_sdma_load_microcode() 485 WREG32(SDMA0_UCODE_DATA + SDMA0_REGISTER_OFFSET, CIK_SDMA_UCODE_VERSION); in cik_sdma_load_microcode() 500 WREG32(SDMA0_UCODE_ADDR + SDMA0_REGISTER_OFFSET, 0); in cik_sdma_load_microcode() [all …]
|
H A D | cik.c | 156 case (SDMA0_STATUS_REG + SDMA0_REGISTER_OFFSET): in cik_get_allowed_info_register() 4847 RREG32(SDMA0_STATUS_REG + SDMA0_REGISTER_OFFSET)); in cik_print_gpu_status_regs() 4901 tmp = RREG32(SDMA0_STATUS_REG + SDMA0_REGISTER_OFFSET); in cik_gpu_check_soft_reset() 4989 tmp = RREG32(SDMA0_ME_CNTL + SDMA0_REGISTER_OFFSET); in cik_gpu_soft_reset() 4991 WREG32(SDMA0_ME_CNTL + SDMA0_REGISTER_OFFSET, tmp); in cik_gpu_soft_reset() 5192 tmp = RREG32(SDMA0_ME_CNTL + SDMA0_REGISTER_OFFSET); in cik_gpu_pci_config_reset() 5194 WREG32(SDMA0_ME_CNTL + SDMA0_REGISTER_OFFSET, tmp); in cik_gpu_pci_config_reset() 5548 WREG32(SDMA0_GFX_APE1_CNTL + SDMA0_REGISTER_OFFSET, 0); in cik_pcie_gart_enable() 6211 WREG32(SDMA0_CLK_CTRL + SDMA0_REGISTER_OFFSET, data); in cik_enable_sdma_mgcg() 6912 WREG32(SDMA0_CNTL + SDMA0_REGISTER_OFFSET, tmp); in cik_disable_interrupt_state() [all …]
|
H A D | cikd.h | 1952 #define SDMA0_REGISTER_OFFSET 0x0 /* not a register */ macro
|
/dragonfly/sys/dev/drm/amd/amdgpu/ |
H A D | sdma_v2_4.c | 59 SDMA0_REGISTER_OFFSET, 1027 tmp = RREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET); in sdma_v2_4_soft_reset() 1029 WREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET, tmp); in sdma_v2_4_soft_reset() 1071 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET); in sdma_v2_4_set_trap_irq_state() 1073 WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl); in sdma_v2_4_set_trap_irq_state() 1076 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET); in sdma_v2_4_set_trap_irq_state() 1078 WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl); in sdma_v2_4_set_trap_irq_state()
|
H A D | sdma_v3_0.c | 73 SDMA0_REGISTER_OFFSET, 1407 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET); in sdma_v3_0_set_trap_irq_state() 1409 WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl); in sdma_v3_0_set_trap_irq_state() 1412 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET); in sdma_v3_0_set_trap_irq_state() 1414 WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl); in sdma_v3_0_set_trap_irq_state()
|
H A D | vid.h | 26 #define SDMA0_REGISTER_OFFSET 0x0 /* not a register */ macro
|
H A D | cikd.h | 486 #define SDMA0_REGISTER_OFFSET 0x0 /* not a register */ macro
|
H A D | vi.c | 481 {mmSDMA0_STATUS_REG + SDMA0_REGISTER_OFFSET},
|