Searched refs:SDMA1_REGISTER_OFFSET (Results 1 – 9 of 9) sorted by relevance
/dragonfly/sys/dev/drm/radeon/ |
H A D | cik_sdma.c | 72 reg = SDMA0_GFX_RB_RPTR + SDMA1_REGISTER_OFFSET; in cik_sdma_get_rptr() 96 reg = SDMA0_GFX_RB_WPTR + SDMA1_REGISTER_OFFSET; in cik_sdma_get_wptr() 117 reg = SDMA0_GFX_RB_WPTR + SDMA1_REGISTER_OFFSET; in cik_sdma_set_wptr() 261 reg_offset = SDMA1_REGISTER_OFFSET; in cik_sdma_gfx_stop() 311 reg_offset = SDMA1_REGISTER_OFFSET; in cik_sdma_ctx_switch_enable() 343 reg_offset = SDMA1_REGISTER_OFFSET; in cik_sdma_enable() 378 reg_offset = SDMA1_REGISTER_OFFSET; in cik_sdma_gfx_resume() 491 WREG32(SDMA0_UCODE_ADDR + SDMA1_REGISTER_OFFSET, 0); in cik_sdma_load_microcode() 494 WREG32(SDMA0_UCODE_DATA + SDMA1_REGISTER_OFFSET, CIK_SDMA_UCODE_VERSION); in cik_sdma_load_microcode() 507 WREG32(SDMA0_UCODE_ADDR + SDMA1_REGISTER_OFFSET, 0); in cik_sdma_load_microcode() [all …]
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H A D | cik.c | 157 case (SDMA0_STATUS_REG + SDMA1_REGISTER_OFFSET): in cik_get_allowed_info_register() 4849 RREG32(SDMA0_STATUS_REG + SDMA1_REGISTER_OFFSET)); in cik_print_gpu_status_regs() 4906 tmp = RREG32(SDMA0_STATUS_REG + SDMA1_REGISTER_OFFSET); in cik_gpu_check_soft_reset() 4995 tmp = RREG32(SDMA0_ME_CNTL + SDMA1_REGISTER_OFFSET); in cik_gpu_soft_reset() 4997 WREG32(SDMA0_ME_CNTL + SDMA1_REGISTER_OFFSET, tmp); in cik_gpu_soft_reset() 5196 tmp = RREG32(SDMA0_ME_CNTL + SDMA1_REGISTER_OFFSET); in cik_gpu_pci_config_reset() 5198 WREG32(SDMA0_ME_CNTL + SDMA1_REGISTER_OFFSET, tmp); in cik_gpu_pci_config_reset() 5550 WREG32(SDMA0_GFX_APE1_CNTL + SDMA1_REGISTER_OFFSET, 0); in cik_pcie_gart_enable() 6216 WREG32(SDMA0_CLK_CTRL + SDMA1_REGISTER_OFFSET, data); in cik_enable_sdma_mgcg() 6914 WREG32(SDMA0_CNTL + SDMA1_REGISTER_OFFSET, tmp); in cik_disable_interrupt_state() [all …]
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H A D | cikd.h | 1953 #define SDMA1_REGISTER_OFFSET 0x800 /* not a register */ macro
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/dragonfly/sys/dev/drm/amd/amdgpu/ |
H A D | sdma_v2_4.c | 60 SDMA1_REGISTER_OFFSET 1034 tmp = RREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET); in sdma_v2_4_soft_reset() 1036 WREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET, tmp); in sdma_v2_4_soft_reset() 1087 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET); in sdma_v2_4_set_trap_irq_state() 1089 WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl); in sdma_v2_4_set_trap_irq_state() 1092 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET); in sdma_v2_4_set_trap_irq_state() 1094 WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl); in sdma_v2_4_set_trap_irq_state()
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H A D | sdma_v3_0.c | 74 SDMA1_REGISTER_OFFSET 1423 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET); in sdma_v3_0_set_trap_irq_state() 1425 WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl); in sdma_v3_0_set_trap_irq_state() 1428 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET); in sdma_v3_0_set_trap_irq_state() 1430 WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl); in sdma_v3_0_set_trap_irq_state()
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H A D | vid.h | 27 #define SDMA1_REGISTER_OFFSET 0x200 /* not a register */ macro
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H A D | cikd.h | 487 #define SDMA1_REGISTER_OFFSET 0x200 /* not a register */ macro
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H A D | amdgpu_amdkfd_gfx_v8.c | 295 retval = m->sdma_engine_id * SDMA1_REGISTER_OFFSET + in get_sdma_base_addr() 491 uint32_t sdma_offset = engine_id * SDMA1_REGISTER_OFFSET + in kgd_hqd_sdma_dump()
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H A D | vi.c | 482 {mmSDMA0_STATUS_REG + SDMA1_REGISTER_OFFSET},
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