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Searched refs:SPI_CONFIG_CNTL (Results 1 – 15 of 15) sorted by relevance

/dragonfly/sys/dev/drm/radeon/
H A Drv770.c1307 WREG32(SPI_CONFIG_CNTL, DISABLE_INTERP_1); in rv770_gpu_init()
1309 WREG32(SPI_CONFIG_CNTL, 0); in rv770_gpu_init()
H A Drv770d.h523 #define SPI_CONFIG_CNTL 0x9100 macro
H A Dnid.h408 #define SPI_CONFIG_CNTL 0x9100 macro
H A Dsid.h1131 #define SPI_CONFIG_CNTL 0x9100 macro
H A Dcikd.h1186 #define SPI_CONFIG_CNTL 0x9100 macro
H A Devergreend.h1020 #define SPI_CONFIG_CNTL 0x9100 macro
H A Dr600d.h444 #define SPI_CONFIG_CNTL 0x9100 macro
H A Devergreen_cs.c3267 case SPI_CONFIG_CNTL: in evergreen_vm_reg_valid()
H A Dcik.c3393 tmp = RREG32(SPI_CONFIG_CNTL); in cik_gpu_init()
3395 WREG32(SPI_CONFIG_CNTL, tmp); in cik_gpu_init()
H A Dr600.c2172 WREG32(SPI_CONFIG_CNTL, GPR_WRITE_PRIORITY(0)); in r600_gpu_init()
H A Devergreen.c3542 WREG32(SPI_CONFIG_CNTL, 0); in evergreen_gpu_init()
H A Dsi.c4432 case SPI_CONFIG_CNTL: in si_vm_reg_valid()
/dragonfly/sys/dev/drm/radeon/reg_srcs/
H A Devergreen51 0x00009100 SPI_CONFIG_CNTL
H A Dcayman38 0x00009100 SPI_CONFIG_CNTL
H A Dr600388 0x00009100 SPI_CONFIG_CNTL