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Searched refs:SPI_CONFIG_CNTL_1 (Results 1 – 16 of 16) sorted by relevance

/dragonfly/sys/dev/drm/radeon/reg_srcs/
H A Devergreen52 0x0000913C SPI_CONFIG_CNTL_1
H A Dcayman39 0x0000913C SPI_CONFIG_CNTL_1
H A Dr600389 0x0000913C SPI_CONFIG_CNTL_1
/dragonfly/sys/dev/drm/radeon/
H A Drv770d.h526 #define SPI_CONFIG_CNTL_1 0x913C macro
H A Dnid.h410 #define SPI_CONFIG_CNTL_1 0x913C macro
H A Dsid.h1133 #define SPI_CONFIG_CNTL_1 0x913C macro
H A Dcikd.h1188 #define SPI_CONFIG_CNTL_1 0x913C macro
H A Drv770.c1453 WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4)); in rv770_gpu_init()
H A Devergreend.h1022 #define SPI_CONFIG_CNTL_1 0x913C macro
H A Dni.c1192 WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4) | CRC_SIMD_ID_WADDR_DISABLE); in cayman_gpu_init()
H A Dr600d.h447 #define SPI_CONFIG_CNTL_1 0x913C macro
H A Dsi.c3302 WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4)); in si_gpu_init()
4433 case SPI_CONFIG_CNTL_1: in si_vm_reg_valid()
H A Devergreen_cs.c3268 case SPI_CONFIG_CNTL_1: in evergreen_vm_reg_valid()
H A Dr600.c2173 WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(0)); in r600_gpu_init()
H A Devergreen.c3543 WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4)); in evergreen_gpu_init()
H A Dcik.c3413 WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4)); in cik_gpu_init()