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Searched refs:UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK (Results 1 – 9 of 9) sorted by relevance

/dragonfly/sys/dev/drm/amd/include/asic_reg/uvd/
H A Duvd_7_0_sh_mask.h442 #define UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK macro
H A Duvd_4_0_sh_mask.h32 #define UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK 0x0000003cL macro
H A Duvd_4_2_sh_mask.h223 #define UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK 0x3c macro
H A Duvd_5_0_sh_mask.h245 #define UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK 0x3c macro
H A Duvd_6_0_sh_mask.h247 #define UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK 0x3c macro
/dragonfly/sys/dev/drm/amd/include/asic_reg/vcn/
H A Dvcn_1_0_sh_mask.h910 #define UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK macro
/dragonfly/sys/dev/drm/amd/amdgpu/
H A Duvd_v5_0.c666 UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK); in uvd_v5_0_set_sw_clock_gating()
H A Duvd_v6_0.c1327 UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK); in uvd_v6_0_set_sw_clock_gating()
H A Duvd_v7_0.c1592 UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK);