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Searched refs:UVD_CGC_CTRL__MPRD_MODE_MASK (Results 1 – 10 of 10) sorted by relevance

/dragonfly/sys/dev/drm/amd/include/asic_reg/uvd/
H A Duvd_7_0_sh_mask.h457 #define UVD_CGC_CTRL__MPRD_MODE_MASK … macro
H A Duvd_4_0_sh_mask.h52 #define UVD_CGC_CTRL__MPRD_MODE_MASK 0x01000000L macro
H A Duvd_4_2_sh_mask.h253 #define UVD_CGC_CTRL__MPRD_MODE_MASK 0x1000000 macro
H A Duvd_5_0_sh_mask.h275 #define UVD_CGC_CTRL__MPRD_MODE_MASK 0x1000000 macro
H A Duvd_6_0_sh_mask.h277 #define UVD_CGC_CTRL__MPRD_MODE_MASK 0x1000000 macro
/dragonfly/sys/dev/drm/amd/include/asic_reg/vcn/
H A Dvcn_1_0_sh_mask.h925 #define UVD_CGC_CTRL__MPRD_MODE_MASK … macro
/dragonfly/sys/dev/drm/amd/amdgpu/
H A Duvd_v5_0.c686 UVD_CGC_CTRL__MPRD_MODE_MASK | in uvd_v5_0_set_sw_clock_gating()
H A Dvcn_v1_0.c399 | UVD_CGC_CTRL__MPRD_MODE_MASK in vcn_v1_0_disable_clock_gating()
500 | UVD_CGC_CTRL__MPRD_MODE_MASK in vcn_v1_0_enable_clock_gating()
H A Duvd_v6_0.c1347 UVD_CGC_CTRL__MPRD_MODE_MASK | in uvd_v6_0_set_sw_clock_gating()
H A Duvd_v7_0.c1617 UVD_CGC_CTRL__MPRD_MODE_MASK |