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Searched refs:UVD_CGC_GATE__IDCT_MASK (Results 1 – 10 of 10) sorted by relevance

/dragonfly/sys/dev/drm/amd/amdgpu/
H A Duvd_v6_0.c642 UVD_CGC_GATE__IDCT_MASK |
675 UVD_CGC_GATE__IDCT_MASK |
1291 UVD_CGC_GATE__IDCT_MASK | in uvd_v6_0_enable_clock_gating()
1379 UVD_CGC_GATE__IDCT_MASK |
H A Duvd_v5_0.c630 UVD_CGC_GATE__IDCT_MASK | in uvd_v5_0_enable_clock_gating()
717 UVD_CGC_GATE__IDCT_MASK |
H A Dvcn_v1_0.c370 | UVD_CGC_GATE__IDCT_MASK in vcn_v1_0_disable_clock_gating()
H A Duvd_v7_0.c1651 UVD_CGC_GATE__IDCT_MASK |
/dragonfly/sys/dev/drm/amd/include/asic_reg/uvd/
H A Duvd_7_0_sh_mask.h404 #define UVD_CGC_GATE__IDCT_MASK macro
H A Duvd_4_0_sh_mask.h78 #define UVD_CGC_GATE__IDCT_MASK 0x00000080L macro
H A Duvd_4_2_sh_mask.h137 #define UVD_CGC_GATE__IDCT_MASK 0x80 macro
H A Duvd_5_0_sh_mask.h149 #define UVD_CGC_GATE__IDCT_MASK 0x80 macro
H A Duvd_6_0_sh_mask.h151 #define UVD_CGC_GATE__IDCT_MASK 0x80 macro
/dragonfly/sys/dev/drm/amd/include/asic_reg/vcn/
H A Dvcn_1_0_sh_mask.h807 #define UVD_CGC_GATE__IDCT_MASK macro