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Searched refs:UVD_CGC_GATE__REGS_MASK (Results 1 – 9 of 9) sorted by relevance

/dragonfly/sys/dev/drm/amd/include/asic_reg/uvd/
H A Duvd_7_0_sh_mask.h400 #define UVD_CGC_GATE__REGS_MASK … macro
H A Duvd_4_0_sh_mask.h96 #define UVD_CGC_GATE__REGS_MASK 0x00000008L macro
H A Duvd_4_2_sh_mask.h129 #define UVD_CGC_GATE__REGS_MASK 0x8 macro
H A Duvd_5_0_sh_mask.h141 #define UVD_CGC_GATE__REGS_MASK 0x8 macro
H A Duvd_6_0_sh_mask.h143 #define UVD_CGC_GATE__REGS_MASK 0x8 macro
/dragonfly/sys/dev/drm/amd/include/asic_reg/vcn/
H A Dvcn_1_0_sh_mask.h803 #define UVD_CGC_GATE__REGS_MASK … macro
/dragonfly/sys/dev/drm/amd/amdgpu/
H A Duvd_v5_0.c646 data3 &= ~UVD_CGC_GATE__REGS_MASK; in uvd_v5_0_enable_clock_gating()
H A Duvd_v6_0.c1309 data3 &= ~UVD_CGC_GATE__REGS_MASK; in uvd_v6_0_enable_clock_gating()
H A Dvcn_v1_0.c366 | UVD_CGC_GATE__REGS_MASK in vcn_v1_0_disable_clock_gating()