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Searched refs:UVD_CGC_GATE__VCPU_MASK (Results 1 – 10 of 10) sorted by relevance

/dragonfly/sys/dev/drm/amd/amdgpu/
H A Duvd_v6_0.c653 UVD_CGC_GATE__VCPU_MASK |
686 UVD_CGC_GATE__VCPU_MASK |
1307 data3 |= UVD_CGC_GATE__VCPU_MASK; in uvd_v6_0_enable_clock_gating()
1390 UVD_CGC_GATE__VCPU_MASK |
H A Duvd_v5_0.c645 data3 |= UVD_CGC_GATE__VCPU_MASK; in uvd_v5_0_enable_clock_gating()
728 UVD_CGC_GATE__VCPU_MASK |
H A Dvcn_v1_0.c381 | UVD_CGC_GATE__VCPU_MASK in vcn_v1_0_disable_clock_gating()
H A Duvd_v7_0.c1662 UVD_CGC_GATE__VCPU_MASK |
/dragonfly/sys/dev/drm/amd/include/asic_reg/uvd/
H A Duvd_7_0_sh_mask.h415 #define UVD_CGC_GATE__VCPU_MASK macro
H A Duvd_4_0_sh_mask.h114 #define UVD_CGC_GATE__VCPU_MASK 0x00040000L macro
H A Duvd_4_2_sh_mask.h159 #define UVD_CGC_GATE__VCPU_MASK 0x40000 macro
H A Duvd_5_0_sh_mask.h171 #define UVD_CGC_GATE__VCPU_MASK 0x40000 macro
H A Duvd_6_0_sh_mask.h173 #define UVD_CGC_GATE__VCPU_MASK 0x40000 macro
/dragonfly/sys/dev/drm/amd/include/asic_reg/vcn/
H A Dvcn_1_0_sh_mask.h818 #define UVD_CGC_GATE__VCPU_MASK macro