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Searched refs:UVD_CGC_STATUS__MPC_SCLK__SHIFT (Results 1 – 5 of 5) sorted by relevance

/dragonfly/sys/dev/drm/amd/include/asic_reg/uvd/
H A Duvd_4_0_sh_mask.h167 #define UVD_CGC_STATUS__MPC_SCLK__SHIFT 0x00000013 macro
H A Duvd_4_2_sh_mask.h202 #define UVD_CGC_STATUS__MPC_SCLK__SHIFT 0x13 macro
H A Duvd_5_0_sh_mask.h218 #define UVD_CGC_STATUS__MPC_SCLK__SHIFT 0x13 macro
H A Duvd_6_0_sh_mask.h220 #define UVD_CGC_STATUS__MPC_SCLK__SHIFT 0x13 macro
/dragonfly/sys/dev/drm/amd/include/asic_reg/vcn/
H A Dvcn_1_0_sh_mask.h840 #define UVD_CGC_STATUS__MPC_SCLK__SHIFT … macro