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Searched refs:UVD_MPC_SET_MUXA0__VARA_0__SHIFT (Results 1 – 6 of 6) sorted by relevance

/dragonfly/sys/dev/drm/amd/include/asic_reg/uvd/
H A Duvd_7_0_sh_mask.h598 #define UVD_MPC_SET_MUXA0__VARA_0__SHIFT … macro
H A Duvd_4_0_sh_mask.h497 #define UVD_MPC_SET_MUXA0__VARA_0__SHIFT 0x00000000 macro
H A Duvd_4_2_sh_mask.h482 #define UVD_MPC_SET_MUXA0__VARA_0__SHIFT 0x0 macro
H A Duvd_5_0_sh_mask.h514 #define UVD_MPC_SET_MUXA0__VARA_0__SHIFT 0x0 macro
H A Duvd_6_0_sh_mask.h516 #define UVD_MPC_SET_MUXA0__VARA_0__SHIFT 0x0 macro
/dragonfly/sys/dev/drm/amd/include/asic_reg/vcn/
H A Dvcn_1_0_sh_mask.h1059 #define UVD_MPC_SET_MUXA0__VARA_0__SHIFT … macro