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Searched refs:UVD_MPC_SET_MUXA0__VARA_4__SHIFT (Results 1 – 6 of 6) sorted by relevance

/dragonfly/sys/dev/drm/amd/include/asic_reg/uvd/
H A Duvd_7_0_sh_mask.h602 #define UVD_MPC_SET_MUXA0__VARA_4__SHIFT … macro
H A Duvd_4_0_sh_mask.h505 #define UVD_MPC_SET_MUXA0__VARA_4__SHIFT 0x00000018 macro
H A Duvd_4_2_sh_mask.h490 #define UVD_MPC_SET_MUXA0__VARA_4__SHIFT 0x18 macro
H A Duvd_5_0_sh_mask.h522 #define UVD_MPC_SET_MUXA0__VARA_4__SHIFT 0x18 macro
H A Duvd_6_0_sh_mask.h524 #define UVD_MPC_SET_MUXA0__VARA_4__SHIFT 0x18 macro
/dragonfly/sys/dev/drm/amd/include/asic_reg/vcn/
H A Dvcn_1_0_sh_mask.h1063 #define UVD_MPC_SET_MUXA0__VARA_4__SHIFT … macro