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Searched refs:UVD_MPC_SET_MUXA1__VARA_7_MASK (Results 1 – 6 of 6) sorted by relevance

/dragonfly/sys/dev/drm/amd/include/asic_reg/uvd/
H A Duvd_7_0_sh_mask.h614 #define UVD_MPC_SET_MUXA1__VARA_7_MASK … macro
H A Duvd_4_0_sh_mask.h510 #define UVD_MPC_SET_MUXA1__VARA_7_MASK 0x0003f000L macro
H A Duvd_4_2_sh_mask.h495 #define UVD_MPC_SET_MUXA1__VARA_7_MASK 0x3f000 macro
H A Duvd_5_0_sh_mask.h527 #define UVD_MPC_SET_MUXA1__VARA_7_MASK 0x3f000 macro
H A Duvd_6_0_sh_mask.h529 #define UVD_MPC_SET_MUXA1__VARA_7_MASK 0x3f000 macro
/dragonfly/sys/dev/drm/amd/include/asic_reg/vcn/
H A Dvcn_1_0_sh_mask.h1075 #define UVD_MPC_SET_MUXA1__VARA_7_MASK … macro