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Searched refs:UVD_SEMA_CMD__MODE_MASK (Results 1 – 5 of 5) sorted by relevance

/dragonfly/sys/dev/drm/amd/include/asic_reg/uvd/
H A Duvd_4_0_sh_mask.h616 #define UVD_SEMA_CMD__MODE_MASK 0x00000040L macro
H A Duvd_4_2_sh_mask.h35 #define UVD_SEMA_CMD__MODE_MASK 0x40 macro
H A Duvd_5_0_sh_mask.h35 #define UVD_SEMA_CMD__MODE_MASK 0x40 macro
H A Duvd_6_0_sh_mask.h35 #define UVD_SEMA_CMD__MODE_MASK 0x40 macro
/dragonfly/sys/dev/drm/amd/include/asic_reg/vcn/
H A Dvcn_1_0_sh_mask.h279 #define UVD_SEMA_CMD__MODE_MASK … macro