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Searched refs:UVD_STATUS__VCPU_REPORT__SHIFT (Results 1 – 9 of 9) sorted by relevance

/dragonfly/sys/dev/drm/amd/include/asic_reg/uvd/
H A Duvd_7_0_sh_mask.h752 #define UVD_STATUS__VCPU_REPORT__SHIFT … macro
H A Duvd_4_0_sh_mask.h693 #define UVD_STATUS__VCPU_REPORT__SHIFT 0x00000001 macro
H A Duvd_4_2_sh_mask.h632 #define UVD_STATUS__VCPU_REPORT__SHIFT 0x1 macro
H A Duvd_5_0_sh_mask.h694 #define UVD_STATUS__VCPU_REPORT__SHIFT 0x1 macro
H A Duvd_6_0_sh_mask.h696 #define UVD_STATUS__VCPU_REPORT__SHIFT 0x1 macro
/dragonfly/sys/dev/drm/amd/include/asic_reg/vcn/
H A Dvcn_1_0_sh_mask.h1229 #define UVD_STATUS__VCPU_REPORT__SHIFT … macro
/dragonfly/sys/dev/drm/amd/amdgpu/
H A Duvd_v7_0.c893 ~(2 << UVD_STATUS__VCPU_REPORT__SHIFT), 0); in uvd_v7_0_sriov_start()
1060 ~(2 << UVD_STATUS__VCPU_REPORT__SHIFT)); in uvd_v7_0_start()
H A Duvd_v6_0.c823 WREG32_P(mmUVD_STATUS, 0, ~(2 << UVD_STATUS__VCPU_REPORT__SHIFT)); in uvd_v6_0_start()
H A Dvcn_v1_0.c730 ~(2 << UVD_STATUS__VCPU_REPORT__SHIFT)); in vcn_v1_0_start()