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Searched refs:UVD_UDEC_DBW_ADDR_CONFIG__NUM_PIPES_MASK (Results 1 – 6 of 6) sorted by relevance

/dragonfly/sys/dev/drm/amd/include/asic_reg/uvd/
H A Duvd_7_0_sh_mask.h193 #define UVD_UDEC_DBW_ADDR_CONFIG__NUM_PIPES_MASK … macro
H A Duvd_4_0_sh_mask.h738 #define UVD_UDEC_DBW_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L macro
H A Duvd_4_2_sh_mask.h91 #define UVD_UDEC_DBW_ADDR_CONFIG__NUM_PIPES_MASK 0x7 macro
H A Duvd_5_0_sh_mask.h91 #define UVD_UDEC_DBW_ADDR_CONFIG__NUM_PIPES_MASK 0x7 macro
H A Duvd_6_0_sh_mask.h91 #define UVD_UDEC_DBW_ADDR_CONFIG__NUM_PIPES_MASK 0x7 macro
/dragonfly/sys/dev/drm/amd/include/asic_reg/vcn/
H A Dvcn_1_0_sh_mask.h390 #define UVD_UDEC_DBW_ADDR_CONFIG__NUM_PIPES_MASK … macro