/dragonfly/sys/dev/drm/radeon/ |
H A D | rs780_dpm.c | 260 WREG32_P(FVTHROT_PWM_CTRL_REG0, in rs780_voltage_scaling_init() 264 WREG32_P(FVTHROT_PWM_CTRL_REG0, in rs780_voltage_scaling_init() 287 WREG32_P(FVTHROT_PWM_FEEDBACK_DIV_REG1, in rs780_voltage_scaling_init() 309 WREG32_P(FVTHROT_CNTRL_REG, 0, in rs780_clk_scaling_enable() 338 WREG32_P(FVTHROT_FBDIV_REG2, in rs780_set_engine_clock_sc() 342 WREG32_P(FVTHROT_CNTRL_REG, in rs780_set_engine_clock_sc() 390 WREG32_P(FVTHROT_PWM_CTRL_REG0, in rs780_force_voltage() 394 WREG32_P(FVTHROT_PWM_CTRL_REG0, in rs780_force_voltage() 462 WREG32_P(FVTHROT_FBDIV_REG0, in rs780_set_engine_clock_scaling() 550 WREG32_P(FVTHROT_PWM_CTRL_REG0, in rs780_enable_voltage_scaling() [all …]
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H A D | r600_dpm.c | 378 WREG32_P(CG_TPC, TPU(u), ~TPU_MASK); in r600_set_tpu() 383 WREG32_P(CG_TPC, TPCC(c), ~TPCC_MASK); in r600_set_tpc() 393 WREG32_P(CG_SSP, CG_SST(t), ~CG_SST_MASK); in r600_set_sst() 403 WREG32_P(CG_FC_T, FC_TU(u), ~FC_TU_MASK); in r600_set_fctu() 408 WREG32_P(CG_FC_T, FC_T(t), ~FC_T_MASK); in r600_set_fct() 423 WREG32_P(CG_VDDC3D_OOR, SU(u), ~SU_MASK); in r600_set_vddc3d_oorsu() 428 WREG32_P(CG_VDDC3D_OOR, PHC(p), ~PHC_MASK); in r600_set_vddc3d_oorphc() 509 WREG32_P(VID_RT, SSTU(u), ~SSTU_MASK); in r600_vid_rt_set_ssu() 580 WREG32_P(CTXSW_PROFILE_INDEX + (ix * 4), in r600_power_level_set_voltage_index() 589 WREG32_P(CTXSW_PROFILE_INDEX + (ix * 4), in r600_power_level_set_mem_clock_index() [all …]
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H A D | uvd_v1_0.c | 227 WREG32_P(UVD_VCPU_CNTL, 0x10, ~0x10); in uvd_v1_0_init() 277 WREG32_P(UVD_MASTINT_EN, 0, ~(1 << 1)); in uvd_v1_0_start() 280 WREG32_P(UVD_LMI_CTRL2, 1 << 8, ~(1 << 8)); in uvd_v1_0_start() 281 WREG32_P(UVD_RB_ARB_CTRL, 1 << 3, ~(1 << 3)); in uvd_v1_0_start() 321 WREG32_P(UVD_LMI_CTRL2, 0, ~(1 << 8)); in uvd_v1_0_start() 323 WREG32_P(UVD_RB_ARB_CTRL, 0, ~(1 << 3)); in uvd_v1_0_start() 355 WREG32_P(UVD_MASTINT_EN, 3<<1, ~(3 << 1)); in uvd_v1_0_start() 397 WREG32_P(UVD_LMI_CTRL2, 1 << 8, ~(1 << 8)); in uvd_v1_0_stop() 398 WREG32_P(UVD_RB_ARB_CTRL, 1 << 3, ~(1 << 3)); in uvd_v1_0_stop() 409 WREG32_P(UVD_LMI_CTRL2, 0, ~(1 << 8)); in uvd_v1_0_stop() [all …]
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H A D | vce_v1_0.c | 223 WREG32_P(VCE_CLOCK_GATING_A, 0, ~(1 << 16)); in vce_v1_0_resume() 225 WREG32_P(VCE_UENC_REG_CLOCK_GATING, 0x3F, ~0x3F); in vce_v1_0_resume() 228 WREG32_P(VCE_LMI_FW_PERIODIC_CTRL, 0x4, ~0x4); in vce_v1_0_resume() 231 WREG32_P(VCE_LMI_CACHE_CTRL, 0x0, ~0x1); in vce_v1_0_resume() 253 WREG32_P(VCE_LMI_CTRL2, 0x0, ~0x100); in vce_v1_0_resume() 296 WREG32_P(VCE_STATUS, 1, ~1); in vce_v1_0_start() 312 WREG32_P(VCE_VCPU_CNTL, VCE_CLK_EN, ~VCE_CLK_EN); in vce_v1_0_start() 314 WREG32_P(VCE_SOFT_RESET, in vce_v1_0_start() 322 WREG32_P(VCE_SOFT_RESET, 0, ~( in vce_v1_0_start() 341 WREG32_P(VCE_SOFT_RESET, 0, ~VCE_ECPU_SOFT_RESET); in vce_v1_0_start() [all …]
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H A D | sumo_dpm.c | 131 WREG32_P(CG_GIT, CG_GICST(p), ~CG_GICST_MASK); in sumo_program_git() 178 WREG32_P(CG_PWR_GATING_CNTL, PGP(p) | PGU(u), in sumo_gfx_powergating_initialize() 184 WREG32_P(CG_CG_VOLTAGE_CNTL, PGP(p) | PGU(u), in sumo_gfx_powergating_initialize() 483 WREG32_P(CG_SCLK_DPM_CTRL + (reg_index * 4), in sumo_set_divider_value() 486 WREG32_P(CG_SCLK_DPM_CTRL + (reg_index * 4), in sumo_set_divider_value() 489 WREG32_P(CG_SCLK_DPM_CTRL + (reg_index * 4), in sumo_set_divider_value() 492 WREG32_P(CG_SCLK_DPM_CTRL + (reg_index * 4), in sumo_set_divider_value() 568 WREG32_P(DEEP_SLEEP_CNTL, 0, ~ENABLE_DS); in sumo_program_power_level() 909 WREG32_P(DEEP_SLEEP_CNTL, 0, ~ENABLE_DS); in sumo_enable_sclk_ds() 915 WREG32_P(CG_AT_0, CG_L(0), ~CG_L_MASK); in sumo_program_bootup_at() [all …]
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H A D | vce_v2_0.c | 162 WREG32_P(VCE_CLOCK_GATING_A, 0, ~(1 << 16)); in vce_v2_0_resume() 163 WREG32_P(VCE_UENC_CLOCK_GATING, 0x1FF000, ~0xFF9FF000); in vce_v2_0_resume() 164 WREG32_P(VCE_UENC_REG_CLOCK_GATING, 0x3F, ~0x3F); in vce_v2_0_resume() 168 WREG32_P(VCE_LMI_CACHE_CTRL, 0x0, ~0x1); in vce_v2_0_resume() 190 WREG32_P(VCE_LMI_CTRL2, 0x0, ~0x100); in vce_v2_0_resume() 192 WREG32_P(VCE_SYS_INT_EN, VCE_SYS_INT_TRAP_INTERRUPT_EN, in vce_v2_0_resume()
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H A D | r600_hdmi.c | 188 WREG32_P(acr_ctl + offset, in r600_hdmi_update_acr() 194 WREG32_P(HDMI0_ACR_32_0 + offset, in r600_hdmi_update_acr() 197 WREG32_P(HDMI0_ACR_32_1 + offset, in r600_hdmi_update_acr() 201 WREG32_P(HDMI0_ACR_44_0 + offset, in r600_hdmi_update_acr() 204 WREG32_P(HDMI0_ACR_44_1 + offset, in r600_hdmi_update_acr() 208 WREG32_P(HDMI0_ACR_48_0 + offset, in r600_hdmi_update_acr() 211 WREG32_P(HDMI0_ACR_48_1 + offset, in r600_hdmi_update_acr() 314 WREG32_P(HDMI0_AUDIO_PACKET_CONTROL + offset, in r600_hdmi_audio_workaround() 378 WREG32_P(HDMI0_INFOFRAME_CONTROL1 + offset, in r600_set_audio_packet() 391 WREG32_P(HDMI0_60958_0 + offset, in r600_set_audio_packet() [all …]
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H A D | rv6xx_dpm.c | 318 WREG32_P(CG_SPLL_SPREAD_SPECTRUM_LOW + (index * 4), in rv6xx_set_engine_spread_spectrum_clk_s() 356 WREG32_P(CG_MPLL_SPREAD_SPECTRUM, SSEN, ~SSEN); in rv6xx_enable_memory_spread_spectrum() 358 WREG32_P(CG_MPLL_SPREAD_SPECTRUM, 0, ~SSEN); in rv6xx_enable_memory_spread_spectrum() 374 WREG32_P(MPLL_FREQ_LEVEL_0 + (index * 4), in rv6xx_memory_clock_entry_enable_post_divider() 383 WREG32_P(MPLL_FREQ_LEVEL_0 + (index * 4), in rv6xx_memory_clock_entry_set_post_divider() 397 WREG32_P(MPLL_FREQ_LEVEL_0 + (index * 4), in rv6xx_memory_clock_entry_set_reference_divider() 403 WREG32_P(VID_RT, BRT(rt), ~BRT_MASK); in rv6xx_vid_response_set_brt() 994 WREG32_P(MCLK_PWRMGT_CNTL, 0, ~USE_DISPLAY_GAP); in rv6xx_enable_display_gap() 1177 WREG32_P(GENERAL_PWRMGT, 0, in rv6xx_enable_backbias() 1240 WREG32_P(GENERAL_PWRMGT, 0, ~BACKBIAS_VALUE); in rv6xx_set_safe_backbias() [all …]
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H A D | dce3_1_afmt.c | 190 WREG32_P(HDMI0_ACR_32_0 + offset, in dce3_2_hdmi_update_acr() 193 WREG32_P(HDMI0_ACR_32_1 + offset, in dce3_2_hdmi_update_acr() 197 WREG32_P(HDMI0_ACR_44_0 + offset, in dce3_2_hdmi_update_acr() 200 WREG32_P(HDMI0_ACR_44_1 + offset, in dce3_2_hdmi_update_acr() 204 WREG32_P(HDMI0_ACR_48_0 + offset, in dce3_2_hdmi_update_acr() 207 WREG32_P(HDMI0_ACR_48_1 + offset, in dce3_2_hdmi_update_acr()
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H A D | rv770_dpm.c | 140 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~DYN_GFX_CLK_OFF_EN); in rv770_gfx_clock_gating_enable() 142 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~GFX_CLK_FORCE_ON); in rv770_gfx_clock_gating_enable() 186 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~SCLK_PWRMGT_OFF); in rv770_start_dpm() 188 WREG32_P(MCLK_PWRMGT_CNTL, 0, ~MPLL_PWRMGT_OFF); in rv770_start_dpm() 202 WREG32_P(GENERAL_PWRMGT, 0, ~GLOBAL_PWRMGT_EN); in rv770_stop_dpm() 798 WREG32_P(CG_SPLL_SPREAD_SPECTRUM, 0, ~SSEN); in rv770_enable_spread_spectrum() 802 WREG32_P(CG_MPLL_SPREAD_SPECTRUM, 0, ~SSEN); in rv770_enable_spread_spectrum() 862 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_TREND_MODE); in rv770_program_tp() 1343 WREG32_P(GENERAL_PWRMGT, 0, ~VOLT_PWRMGT_EN); in rv770_enable_voltage_control() 1372 WREG32_P(GENERAL_PWRMGT, 0, ~ENABLE_GEN2PCIE); in rv770_enable_dynamic_pcie_gen2() [all …]
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H A D | cypress_dpm.c | 94 WREG32_P(GENERAL_PWRMGT, 0, ~ENABLE_GEN2PCIE); in cypress_enable_dynamic_pcie_gen2() 103 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~DYN_GFX_CLK_OFF_EN); 105 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~GFX_CLK_FORCE_ON); 145 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~DYN_GFX_CLK_OFF_EN); in cypress_gfx_clock_gating_enable() 147 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~GFX_CLK_FORCE_ON); in cypress_gfx_clock_gating_enable() 230 WREG32_P(MPLL_CNTL_MODE, SS_SSEN, ~SS_SSEN); in cypress_enable_spread_spectrum() 232 WREG32_P(CG_SPLL_SPREAD_SPECTRUM, 0, ~SSEN); in cypress_enable_spread_spectrum() 234 WREG32_P(MPLL_CNTL_MODE, 0, ~SS_SSEN); in cypress_enable_spread_spectrum() 235 WREG32_P(MPLL_CNTL_MODE, 0, ~SS_DSMODE_EN); in cypress_enable_spread_spectrum() 248 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~SCLK_PWRMGT_OFF); in cypress_enable_sclk_control() [all …]
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H A D | rv770_smc.c | 394 WREG32_P(SMC_IO, SMC_RST_N, ~SMC_RST_N); in rv770_start_smc() 399 WREG32_P(SMC_IO, 0, ~SMC_RST_N); in rv770_reset_smc() 404 WREG32_P(SMC_IO, 0, ~SMC_CLK_EN); in rv770_stop_smc_clock() 409 WREG32_P(SMC_IO, SMC_CLK_EN, ~SMC_CLK_EN); in rv770_start_smc_clock() 433 WREG32_P(SMC_MSG, HOST_SMC_MSG(msg), ~HOST_SMC_MSG_MASK); in rv770_send_msg_to_smc()
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H A D | rv770.c | 54 WREG32_P(CG_UPLL_FUNC_CNTL_2, in rv770_set_uvd_clocks() 60 WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_SLEEP_MASK, ~UPLL_SLEEP_MASK); in rv770_set_uvd_clocks() 82 WREG32_P(CG_UPLL_FUNC_CNTL_3, UPLL_FB_DIV(1), ~UPLL_FB_DIV(1)); in rv770_set_uvd_clocks() 89 WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_RESET_MASK, ~UPLL_RESET_MASK); in rv770_set_uvd_clocks() 92 WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_REF_DIV(1), ~UPLL_REF_DIV_MASK); in rv770_set_uvd_clocks() 93 WREG32_P(CG_UPLL_FUNC_CNTL_2, in rv770_set_uvd_clocks() 100 WREG32_P(CG_UPLL_FUNC_CNTL_3, UPLL_FB_DIV(fb_div), in rv770_set_uvd_clocks() 107 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_RESET_MASK); in rv770_set_uvd_clocks() 112 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_BYPASS_EN_MASK); in rv770_set_uvd_clocks() 113 WREG32_P(CG_UPLL_FUNC_CNTL_3, 0, ~UPLL_FB_DIV(1)); in rv770_set_uvd_clocks() [all …]
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H A D | ci_smc.c | 42 WREG32_P(SMC_IND_ACCESS_CNTL, 0, ~AUTO_INCREMENT_IND_0); in ci_set_smc_sram_address() 230 WREG32_P(SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_0, ~AUTO_INCREMENT_IND_0); in ci_load_smc_ucode() 240 WREG32_P(SMC_IND_ACCESS_CNTL, 0, ~AUTO_INCREMENT_IND_0); in ci_load_smc_ucode()
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H A D | radeon_legacy_crtc.c | 328 WREG32_P(RADEON_CRTC2_GEN_CNTL, RADEON_CRTC2_EN, ~(RADEON_CRTC2_EN | mask)); in radeon_crtc_dpms() 330 WREG32_P(RADEON_CRTC_GEN_CNTL, RADEON_CRTC_EN, ~(RADEON_CRTC_EN | in radeon_crtc_dpms() 332 WREG32_P(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl, ~(mask | crtc_ext_cntl)); in radeon_crtc_dpms() 344 WREG32_P(RADEON_CRTC2_GEN_CNTL, mask, ~(RADEON_CRTC2_EN | mask)); in radeon_crtc_dpms() 346 WREG32_P(RADEON_CRTC_GEN_CNTL, RADEON_CRTC_DISP_REQ_EN_B, ~(RADEON_CRTC_EN | in radeon_crtc_dpms() 348 WREG32_P(RADEON_CRTC_EXT_CNTL, mask, ~(mask | crtc_ext_cntl)); in radeon_crtc_dpms() 940 WREG32_P(RADEON_CLOCK_CNTL_INDEX, in radeon_set_pll() 961 WREG32_P(RADEON_CLOCK_CNTL_INDEX, in radeon_set_pll()
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H A D | rv730_dpm.c | 453 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~SCLK_PWRMGT_OFF); in rv730_start_dpm() 455 WREG32_P(TCI_MCLK_PWRMGT_CNTL, 0, ~MPLL_PWRMGT_OFF); in rv730_start_dpm() 457 WREG32_P(GENERAL_PWRMGT, GLOBAL_PWRMGT_EN, ~GLOBAL_PWRMGT_EN); in rv730_start_dpm() 469 WREG32_P(GENERAL_PWRMGT, 0, ~GLOBAL_PWRMGT_EN); in rv730_stop_dpm() 471 WREG32_P(SCLK_PWRMGT_CNTL, SCLK_PWRMGT_OFF, ~SCLK_PWRMGT_OFF); in rv730_stop_dpm() 473 WREG32_P(TCI_MCLK_PWRMGT_CNTL, MPLL_PWRMGT_OFF, ~MPLL_PWRMGT_OFF); in rv730_stop_dpm()
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H A D | si_smc.c | 42 WREG32_P(SMC_IND_ACCESS_CNTL, 0, ~AUTO_INCREMENT_IND_0); in si_set_smc_sram_address() 266 WREG32_P(SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_0, ~AUTO_INCREMENT_IND_0); in si_load_smc_ucode() 276 WREG32_P(SMC_IND_ACCESS_CNTL, 0, ~AUTO_INCREMENT_IND_0); in si_load_smc_ucode()
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H A D | trinity_dpm.c | 394 WREG32_P(CG_GIPOTS, CG_GIPOT(p), ~CG_GIPOT_MASK); in trinity_gfx_powergating_initialize() 453 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~DYN_GFX_CLK_OFF_EN); in trinity_gfx_clockgating_enable() 454 WREG32_P(SCLK_PWRMGT_CNTL, GFX_CLK_FORCE_ON, ~GFX_CLK_FORCE_ON); in trinity_gfx_clockgating_enable() 455 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~GFX_CLK_FORCE_ON); in trinity_gfx_clockgating_enable() 466 WREG32_P(seq[i], seq[i+1], ~seq[i+2]); in trinity_program_clk_gating_hw_sequence() 514 WREG32_P(SCLK_PWRMGT_CNTL, DYN_PWR_DOWN_EN, ~DYN_PWR_DOWN_EN); in trinity_gfx_powergating_enable() 516 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~DYN_PWR_DOWN_EN); in trinity_gfx_powergating_enable() 767 WREG32_P(GENERAL_PWRMGT, GLOBAL_PWRMGT_EN, ~GLOBAL_PWRMGT_EN); in trinity_start_dpm() 768 WREG32_P(CG_CG_VOLTAGE_CNTL, 0, ~EN); in trinity_start_dpm() 798 WREG32_P(CG_CG_VOLTAGE_CNTL, EN, ~EN); in trinity_stop_dpm() [all …]
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H A D | evergreen.c | 1181 WREG32_P(CG_UPLL_FUNC_CNTL_2, in evergreen_set_uvd_clocks() 1205 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_SLEEP_MASK); in evergreen_set_uvd_clocks() 1208 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_RESET_MASK); in evergreen_set_uvd_clocks() 1220 WREG32_P(CG_UPLL_SPREAD_SPECTRUM, 0, ~SSEN_MASK); in evergreen_set_uvd_clocks() 1226 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_REF_DIV_MASK); in evergreen_set_uvd_clocks() 1229 WREG32_P(CG_UPLL_FUNC_CNTL_4, 0, ~UPLL_SPARE_ISPARE9); in evergreen_set_uvd_clocks() 1234 WREG32_P(CG_UPLL_FUNC_CNTL_2, in evergreen_set_uvd_clocks() 1242 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_RESET_MASK); in evergreen_set_uvd_clocks() 1247 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_BYPASS_EN_MASK); in evergreen_set_uvd_clocks() 1254 WREG32_P(CG_UPLL_FUNC_CNTL_2, in evergreen_set_uvd_clocks() [all …]
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/dragonfly/sys/dev/drm/amd/amdgpu/ |
H A D | uvd_v5_0.c | 303 WREG32_P(mmUVD_POWER_STATUS, 0, ~(1 << 2)); in uvd_v5_0_start() 312 WREG32_P(mmUVD_MASTINT_EN, 0, ~(1 << 1)); in uvd_v5_0_start() 315 WREG32_P(mmUVD_LMI_CTRL2, 1 << 8, ~(1 << 8)); in uvd_v5_0_start() 357 WREG32_P(mmUVD_LMI_CTRL2, 0, ~(1 << 8)); in uvd_v5_0_start() 376 WREG32_P(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK, in uvd_v5_0_start() 389 WREG32_P(mmUVD_MASTINT_EN, 3 << 1, ~(3 << 1)); in uvd_v5_0_start() 392 WREG32_P(mmUVD_STATUS, 0, ~(2 << 1)); in uvd_v5_0_start() 423 WREG32_P(mmUVD_RBC_RB_CNTL, 0, ~UVD_RBC_RB_CNTL__RB_NO_FETCH_MASK); in uvd_v5_0_start() 441 WREG32_P(mmUVD_LMI_CTRL2, 1 << 8, ~(1 << 8)); in uvd_v5_0_stop() 452 WREG32_P(mmUVD_LMI_CTRL2, 0, ~(1 << 8)); in uvd_v5_0_stop() [all …]
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H A D | vce_v4_0.c | 139 WREG32_P(SOC15_REG_OFFSET(VCE, 0, mmVCE_SOFT_RESET), in vce_v4_0_firmware_loaded() 143 WREG32_P(SOC15_REG_OFFSET(VCE, 0, mmVCE_SOFT_RESET), 0, in vce_v4_0_firmware_loaded() 363 WREG32_P(SOC15_REG_OFFSET(VCE, 0, mmVCE_VCPU_CNTL), 1, ~0x200001); in vce_v4_0_start() 365 WREG32_P(SOC15_REG_OFFSET(VCE, 0, mmVCE_SOFT_RESET), 0, in vce_v4_0_start() 385 WREG32_P(SOC15_REG_OFFSET(VCE, 0, mmVCE_VCPU_CNTL), 0, ~0x200001); in vce_v4_0_stop() 388 WREG32_P(SOC15_REG_OFFSET(VCE, 0, mmVCE_SOFT_RESET), in vce_v4_0_stop() 605 WREG32_P(SOC15_REG_OFFSET(VCE, 0, mmVCE_CLOCK_GATING_A), 0, ~(1 << 16)); in vce_v4_0_mc_resume() 611 WREG32_P(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_CACHE_CTRL), 0x0, ~0x1); in vce_v4_0_mc_resume() 647 WREG32_P(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_CTRL2), 0x0, ~0x100); in vce_v4_0_mc_resume() 648 WREG32_P(SOC15_REG_OFFSET(VCE, 0, mmVCE_SYS_INT_EN), in vce_v4_0_mc_resume() [all …]
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H A D | vce_v3_0.c | 307 WREG32_P(mmVCE_VCPU_CNTL, 1, ~0x200001); in vce_v3_0_start() 344 WREG32_P(mmVCE_VCPU_CNTL, 0, ~0x200001); in vce_v3_0_stop() 534 WREG32_P(mmVCE_CLOCK_GATING_A, 0, ~(1 << 16)); in vce_v3_0_mc_resume() 535 WREG32_P(mmVCE_UENC_CLOCK_GATING, 0x1FF000, ~0xFF9FF000); in vce_v3_0_mc_resume() 536 WREG32_P(mmVCE_UENC_REG_CLOCK_GATING, 0x3F, ~0x3F); in vce_v3_0_mc_resume() 540 WREG32_P(mmVCE_LMI_CACHE_CTRL, 0x0, ~0x1); in vce_v3_0_mc_resume() 577 WREG32_P(mmVCE_LMI_CTRL2, 0x0, ~0x100); in vce_v3_0_mc_resume() 717 WREG32_P(mmVCE_SYS_INT_EN, val, ~VCE_SYS_INT_EN__VCE_SYS_INT_TRAP_INTERRUPT_EN_MASK); in vce_v3_0_set_interrupt_state()
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H A D | uvd_v7_0.c | 959 WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_CGC_CTRL), 0, in uvd_v7_0_start() 963 WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_MASTINT_EN), 0, in uvd_v7_0_start() 967 WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_LMI_CTRL2), in uvd_v7_0_start() 1018 WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_LMI_CTRL2), 0, in uvd_v7_0_start() 1039 WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_SOFT_RESET), in uvd_v7_0_start() 1043 WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_SOFT_RESET), 0, in uvd_v7_0_start() 1054 WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_MASTINT_EN), in uvd_v7_0_start() 1059 WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_STATUS), 0, in uvd_v7_0_start() 1092 WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_RBC_RB_CNTL), 0, in uvd_v7_0_start() 1130 WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_CTRL2), in uvd_v7_0_stop() [all …]
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H A D | vcn_v1_0.c | 635 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_MASTINT_EN), 0, in vcn_v1_0_start() 639 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_CTRL2), in vcn_v1_0_start() 688 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_CTRL2), 0, in vcn_v1_0_start() 709 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), in vcn_v1_0_start() 713 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 0, in vcn_v1_0_start() 724 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_MASTINT_EN), in vcn_v1_0_start() 729 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_STATUS), 0, in vcn_v1_0_start() 762 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_RBC_RB_CNTL), 0, in vcn_v1_0_start() 811 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_CTRL2), in vcn_v1_0_stop() 825 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_CTRL2), 0, in vcn_v1_0_stop()
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H A D | si_dpm.c | 3765 WREG32_P(GENERAL_PWRMGT, 0, ~THERMAL_PROTECTION_DIS); in si_set_dpm_event_sources() 3797 WREG32_P(GENERAL_PWRMGT, 0, ~GLOBAL_PWRMGT_EN); in si_stop_dpm() 3803 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~SCLK_PWRMGT_OFF); in si_enable_sclk_control() 4051 WREG32_P(GENERAL_PWRMGT, 0, ~THERMAL_PROTECTION_DIS); in si_enable_thermal_protection() 4058 WREG32_P(GENERAL_PWRMGT, STATIC_PM_EN, ~STATIC_PM_EN); in si_enable_acpi_power_management() 4141 WREG32_P(CG_SPLL_AUTOSCALE_CNTL, AUTOSCALE_ON_SS_CLEAR, in si_program_ds_registers() 4199 WREG32_P(CG_SPLL_SPREAD_SPECTRUM, 0, ~SSEN); in si_enable_spread_spectrum() 4200 WREG32_P(GENERAL_PWRMGT, 0, ~DYN_SPREAD_SPECTRUM_EN); in si_enable_spread_spectrum() 4242 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_FORCE_TREND_SEL); in si_program_tp() 4247 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_TREND_MODE); in si_program_tp() [all …]
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