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Searched refs:WRITE_DATA_DST_SEL (Results 1 – 9 of 9) sorted by relevance

/dragonfly/sys/dev/drm/amd/amdgpu/
H A Dsoc15d.h110 #define WRITE_DATA_DST_SEL(x) ((x) << 8) macro
H A Dvid.h144 #define WRITE_DATA_DST_SEL(x) ((x) << 8) macro
H A Dcikd.h262 #define WRITE_DATA_DST_SEL(x) ((x) << 8) macro
H A Dgfx_v8_0.c903 ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM; in gfx_v8_0_ring_test_ib()
5459 WRITE_DATA_DST_SEL(0))); in gfx_v8_0_ring_emit_gds_switch()
5467 WRITE_DATA_DST_SEL(0))); in gfx_v8_0_ring_emit_gds_switch()
5475 WRITE_DATA_DST_SEL(0))); in gfx_v8_0_ring_emit_gds_switch()
5483 WRITE_DATA_DST_SEL(0))); in gfx_v8_0_ring_emit_gds_switch()
6626 WRITE_DATA_DST_SEL(5) | WR_CONFIRM)); in gfx_v8_0_ring_emit_fence_kiq()
6635 WRITE_DATA_DST_SEL(0) | WR_CONFIRM)); in gfx_v8_0_ring_emit_fence_kiq()
7481 WRITE_DATA_DST_SEL(8) | in gfx_v8_0_ring_emit_ce_meta()
7514 WRITE_DATA_DST_SEL(8) | in gfx_v8_0_ring_emit_de_meta()
H A Dgfx_v9_0.c310 WRITE_DATA_DST_SEL(0) | in gfx_v9_0_write_data_to_reg()
409 ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM; in gfx_v9_0_ring_test_ib()
4160 WRITE_DATA_DST_SEL(5) | WR_CONFIRM)); in gfx_v9_0_ring_emit_fence_kiq()
4169 WRITE_DATA_DST_SEL(0) | WR_CONFIRM)); in gfx_v9_0_ring_emit_fence_kiq()
4193 WRITE_DATA_DST_SEL(8) | in gfx_v9_0_ring_emit_ce_meta()
4215 WRITE_DATA_DST_SEL(8) | in gfx_v9_0_ring_emit_de_meta()
/dragonfly/sys/dev/drm/radeon/
H A Dsid.h1637 #define WRITE_DATA_DST_SEL(x) ((x) << 8) macro
H A Dcik.c3782 radeon_ring_write(ring, WRITE_DATA_DST_SEL(1)); in cik_ring_ib_execute()
5720 WRITE_DATA_DST_SEL(0))); in cik_vm_flush()
5734 WRITE_DATA_DST_SEL(0))); in cik_vm_flush()
5741 WRITE_DATA_DST_SEL(0))); in cik_vm_flush()
5752 WRITE_DATA_DST_SEL(0))); in cik_vm_flush()
5763 WRITE_DATA_DST_SEL(0))); in cik_vm_flush()
H A Dcikd.h1728 #define WRITE_DATA_DST_SEL(x) ((x) << 8) macro
H A Dsi.c5068 WRITE_DATA_DST_SEL(0))); in si_vm_flush()
5083 WRITE_DATA_DST_SEL(0))); in si_vm_flush()
5091 WRITE_DATA_DST_SEL(0))); in si_vm_flush()