Searched refs:WRITE_DATA_DST_SEL (Results 1 – 9 of 9) sorted by relevance
110 #define WRITE_DATA_DST_SEL(x) ((x) << 8) macro
144 #define WRITE_DATA_DST_SEL(x) ((x) << 8) macro
262 #define WRITE_DATA_DST_SEL(x) ((x) << 8) macro
903 ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM; in gfx_v8_0_ring_test_ib()5459 WRITE_DATA_DST_SEL(0))); in gfx_v8_0_ring_emit_gds_switch()5467 WRITE_DATA_DST_SEL(0))); in gfx_v8_0_ring_emit_gds_switch()5475 WRITE_DATA_DST_SEL(0))); in gfx_v8_0_ring_emit_gds_switch()5483 WRITE_DATA_DST_SEL(0))); in gfx_v8_0_ring_emit_gds_switch()6626 WRITE_DATA_DST_SEL(5) | WR_CONFIRM)); in gfx_v8_0_ring_emit_fence_kiq()6635 WRITE_DATA_DST_SEL(0) | WR_CONFIRM)); in gfx_v8_0_ring_emit_fence_kiq()7481 WRITE_DATA_DST_SEL(8) | in gfx_v8_0_ring_emit_ce_meta()7514 WRITE_DATA_DST_SEL(8) | in gfx_v8_0_ring_emit_de_meta()
310 WRITE_DATA_DST_SEL(0) | in gfx_v9_0_write_data_to_reg()409 ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM; in gfx_v9_0_ring_test_ib()4160 WRITE_DATA_DST_SEL(5) | WR_CONFIRM)); in gfx_v9_0_ring_emit_fence_kiq()4169 WRITE_DATA_DST_SEL(0) | WR_CONFIRM)); in gfx_v9_0_ring_emit_fence_kiq()4193 WRITE_DATA_DST_SEL(8) | in gfx_v9_0_ring_emit_ce_meta()4215 WRITE_DATA_DST_SEL(8) | in gfx_v9_0_ring_emit_de_meta()
1637 #define WRITE_DATA_DST_SEL(x) ((x) << 8) macro
3782 radeon_ring_write(ring, WRITE_DATA_DST_SEL(1)); in cik_ring_ib_execute()5720 WRITE_DATA_DST_SEL(0))); in cik_vm_flush()5734 WRITE_DATA_DST_SEL(0))); in cik_vm_flush()5741 WRITE_DATA_DST_SEL(0))); in cik_vm_flush()5752 WRITE_DATA_DST_SEL(0))); in cik_vm_flush()5763 WRITE_DATA_DST_SEL(0))); in cik_vm_flush()
1728 #define WRITE_DATA_DST_SEL(x) ((x) << 8) macro
5068 WRITE_DATA_DST_SEL(0))); in si_vm_flush()5083 WRITE_DATA_DST_SEL(0))); in si_vm_flush()5091 WRITE_DATA_DST_SEL(0))); in si_vm_flush()