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Searched refs:WR_CONFIRM (Results 1 – 7 of 7) sorted by relevance

/dragonfly/sys/dev/drm/amd/amdgpu/
H A Dsoc15d.h119 #define WR_CONFIRM (1 << 20) macro
H A Dvid.h153 #define WR_CONFIRM (1 << 20) macro
H A Dcikd.h271 #define WR_CONFIRM (1 << 20) macro
H A Dgfx_v9_0.c311 (wc ? WR_CONFIRM : 0)); in gfx_v9_0_write_data_to_reg()
409 ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM; in gfx_v9_0_ring_test_ib()
4160 WRITE_DATA_DST_SEL(5) | WR_CONFIRM)); in gfx_v9_0_ring_emit_fence_kiq()
4169 WRITE_DATA_DST_SEL(0) | WR_CONFIRM)); in gfx_v9_0_ring_emit_fence_kiq()
4194 WR_CONFIRM) | in gfx_v9_0_ring_emit_ce_meta()
4216 WR_CONFIRM) | in gfx_v9_0_ring_emit_de_meta()
4311 cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM; in gfx_v9_0_ring_emit_wreg()
4317 cmd = WR_CONFIRM; in gfx_v9_0_ring_emit_wreg()
H A Dgfx_v8_0.c903 ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM; in gfx_v8_0_ring_test_ib()
6626 WRITE_DATA_DST_SEL(5) | WR_CONFIRM)); in gfx_v8_0_ring_emit_fence_kiq()
6635 WRITE_DATA_DST_SEL(0) | WR_CONFIRM)); in gfx_v8_0_ring_emit_fence_kiq()
6731 cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM; in gfx_v8_0_ring_emit_wreg()
6737 cmd = WR_CONFIRM; in gfx_v8_0_ring_emit_wreg()
7482 WR_CONFIRM) | in gfx_v8_0_ring_emit_ce_meta()
7515 WR_CONFIRM) | in gfx_v8_0_ring_emit_de_meta()
/dragonfly/sys/dev/drm/radeon/
H A Dsid.h1646 #define WR_CONFIRM (1 << 20) macro
H A Dcikd.h1737 #define WR_CONFIRM (1 << 20) macro