| /dragonfly/contrib/gcc-8.0/gcc/config/i386/ |
| H A D | btver2.md | 99 (and (eq_attr "cpu" "btver2")
107 (and (eq_attr "cpu" "btver2")
113 (and (eq_attr "cpu" "btver2")
118 (and (eq_attr "cpu" "btver2")
124 (and (eq_attr "cpu" "btver2")
129 (and (eq_attr "cpu" "btver2")
134 (and (eq_attr "cpu" "btver2")
140 (and (eq_attr "cpu" "btver2")
142 (and (eq_attr "mode" "DI")
147 (and (eq_attr "cpu" "btver2")
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| H A D | znver1.md | 29 ;; and vector type instructions.
82 (and (eq_attr "cpu" "znver1")
88 (and (eq_attr "cpu" "znver1")
94 (and (eq_attr "cpu" "znver1")
100 (and (eq_attr "cpu" "znver1")
106 (and (eq_attr "cpu" "znver1")
112 (and (eq_attr "cpu" "znver1")
119 (and (eq_attr "cpu" "znver1")
127 (and (eq_attr "cpu" "znver1")
133 (and (eq_attr "cpu" "znver1")
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| H A D | slm.md | 80 (and (eq_attr "cpu" "slm")
87 (and (eq_attr "cpu" "slm")
93 (and (eq_attr "cpu" "slm")
99 (and (eq_attr "cpu" "slm")
107 (and (eq_attr "cpu" "slm")
115 (and (eq_attr "cpu" "slm")
123 (and (eq_attr "cpu" "slm")
135 ;; bsf and bsf insn
466 ;; pmad, psad and 64
475 ;; pmad, psad and 128
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| H A D | bdver3.md | 19 ;; AMD bdver3 and bdver4 Scheduling
21 ;; The bdver3 and bdver4 contains three pipelined FP units and two integer
132 (and (eq_attr "mode" "DI")
143 (and (eq_attr "mode" "DI")
154 (and (eq_attr "type" "str")
308 (and (eq_attr "movu" "1")
315 (and (eq_attr "movu" "1")
322 (and (eq_attr "movu" "1")
348 (and (eq_attr "mode" "DI")
411 (and (eq_attr "mode" "V8SF")
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| H A D | haswell.md | 1 ;; Scheduling for Haswell and derived processors.
274 (and (eq_attr "mode" "!XF")
281 (and (eq_attr "mode" "XF")
288 (and (eq_attr "mode" "!XF")
295 (and (eq_attr "mode" "XF")
319 (and (eq_attr "mode" "SF")
326 (and (eq_attr "mode" "SF")
333 (and (eq_attr "mode" "DF")
340 (and (eq_attr "mode" "DF")
347 (and (eq_attr "mode" "XF")
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| H A D | athlon.md | 97 ;; Agu and ieu unit results in extremely large automatons and
177 (and (eq_attr "cpu" "k8")
579 (and (eq_attr "cpu" "k8")
584 (and (eq_attr "cpu" "k8")
602 (and (eq_attr "cpu" "k8")
613 (and (eq_attr "cpu" "k8")
617 ;; On AMDFAM10 all double, single and integer packed and scalar SSEx data
635 (and (eq_attr "cpu" "k8")
641 (and (eq_attr "cpu" "k8")
662 ;; On AMDFAM10 all double, single and integer scalar SSEx and MMX
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| H A D | bdver1.md | 157 (and (eq_attr "type" "imul")
158 (and (eq_attr "mode" "DI")
163 (and (eq_attr "type" "imul")
169 (and (eq_attr "mode" "DI")
201 (and (eq_attr "type" "str")
383 (and (eq_attr "movu" "1")
390 (and (eq_attr "movu" "1")
397 (and (eq_attr "movu" "1")
423 (and (eq_attr "mode" "DI")
486 (and (eq_attr "mode" "V8SF")
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| H A D | core2.md | 1 ;; Scheduling for Core 2 and derived processors.
201 ;; and SImode, port 0 for DImode.
219 (and (eq_attr "mode" "DI")
226 (and (eq_attr "mode" "DI")
231 ;; QI, HI, and SI have issue latency 12, 21, and 37, respectively.
236 (and (eq_attr "mode" "QI")
243 (and (eq_attr "mode" "QI")
250 (and (eq_attr "mode" "HI")
257 (and (eq_attr "mode" "HI")
264 (and (eq_attr "mode" "SI")
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| H A D | atom.md | 88 (and (eq_attr "cpu" "atom")
95 (and (eq_attr "cpu" "atom")
101 (and (eq_attr "cpu" "atom")
107 (and (eq_attr "cpu" "atom")
115 (and (eq_attr "cpu" "atom")
123 (and (eq_attr "cpu" "atom")
131 (and (eq_attr "cpu" "atom")
138 (and (eq_attr "cpu" "atom")
467 ;; pmad, psad and 64
476 ;; pmad, psad and 128
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| H A D | ppro.md | 182 ;; Shift and rotate execute on port 0 with latency and throughput 1.
247 ;; QI, HI, and SI have issue latency 12, 21, and 37, respectively.
252 (and (eq_attr "mode" "QI")
259 (and (eq_attr "mode" "QI")
266 (and (eq_attr "mode" "HI")
273 (and (eq_attr "mode" "HI")
280 (and (eq_attr "mode" "SI")
287 (and (eq_attr "mode" "SI")
362 (and (eq_attr "mode" "XF")
376 (and (eq_attr "mode" "XF")
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| H A D | k6.md | 80 (and (eq_attr "cpu" "k6")
86 (and (eq_attr "cpu" "k6")
92 (and (eq_attr "cpu" "k6")
99 (and (eq_attr "cpu" "k6")
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117 (and (eq_attr "cpu" "k6")
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130 (and (eq_attr "cpu" "k6")
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| H A D | pentium.md | 49 (and (eq_attr "type" "ishift")
52 (and (eq_attr "type" "rotate")
55 (and (eq_attr "type" "ishift1")
58 (and (eq_attr "type" "rotate1")
61 (and (eq_attr "type" "call")
64 (and (eq_attr "type" "callv")
135 (and (eq_attr "cpu" "pentium")
140 (and (eq_attr "cpu" "pentium")
149 (and (eq_attr "cpu" "pentium")
179 ;; Push and pop instructions have 1 cycle latency and special
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| H A D | geode.md | 40 ;; using memory and registers.
47 (and (eq_attr "cpu" "geode")
52 (and (eq_attr "cpu" "geode")
57 (and (eq_attr "cpu" "geode")
62 (and (eq_attr "cpu" "geode")
68 (and (eq_attr "cpu" "geode")
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| H A D | i386.opt | 650 Support MMX and SSE built-in functions and code generation.
654 Support MMX, SSE and SSE2 built-in functions and code generation.
658 Support MMX, SSE, SSE2 and SSE3 built-in functions and code generation.
678 Do not support SSE4.1 and SSE4.2 built-in functions and code generation.
698 …X, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2 and AVX512F and AVX512PF built-in functions a…
702 …X, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2 and AVX512F and AVX512ER built-in functions a…
706 …X, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2 and AVX512F and AVX512CD built-in functions a…
710 …X, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2 and AVX512F and AVX512DQ built-in functions a…
894 Support SHA1 and SHA256 built-in functions and code generation.
959 Support MWAITX and MONITORX built-in functions and code generation.
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| /dragonfly/contrib/gcc-4.7/gcc/config/i386/ |
| H A D | athlon.md | 98 ;; Agu and ieu unit results in extremely large automatons and
186 (and (eq_attr "cpu" "athlon")
207 (and (eq_attr "cpu" "athlon")
215 (and (eq_attr "mode" "DI")
226 (and (eq_attr "mode" "HI")
230 (and (eq_attr "cpu" "athlon")
580 (and (eq_attr "cpu" "k8")
623 ;; On AMDFAM10 all double, single and integer packed and scalar SSEx data
668 ;; On AMDFAM10 all double, single and integer scalar SSEx and MMX
862 (and (eq_attr "mode" "DF")
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| H A D | bdver1.md | 153 (and (eq_attr "type" "imul")
154 (and (eq_attr "mode" "DI")
159 (and (eq_attr "type" "imul")
165 (and (eq_attr "mode" "DI")
197 (and (eq_attr "type" "str")
379 (and (eq_attr "movu" "1")
386 (and (eq_attr "movu" "1")
393 (and (eq_attr "movu" "1")
419 (and (eq_attr "mode" "DI")
482 (and (eq_attr "mode" "V8SF")
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| H A D | core2.md | 1 ;; Scheduling for Core 2 and derived processors.
201 ;; and SImode, port 0 for DImode.
219 (and (eq_attr "mode" "DI")
226 (and (eq_attr "mode" "DI")
231 ;; QI, HI, and SI have issue latency 12, 21, and 37, respectively.
236 (and (eq_attr "mode" "QI")
243 (and (eq_attr "mode" "QI")
250 (and (eq_attr "mode" "HI")
257 (and (eq_attr "mode" "HI")
264 (and (eq_attr "mode" "SI")
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| H A D | atom.md | 88 (and (eq_attr "cpu" "atom")
95 (and (eq_attr "cpu" "atom")
101 (and (eq_attr "cpu" "atom")
107 (and (eq_attr "cpu" "atom")
115 (and (eq_attr "cpu" "atom")
123 (and (eq_attr "cpu" "atom")
131 (and (eq_attr "cpu" "atom")
138 (and (eq_attr "cpu" "atom")
467 ;; pmad, psad and 64
476 ;; pmad, psad and 128
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| H A D | ppro.md | 182 ;; Shift and rotate execute on port 0 with latency and throughput 1.
247 ;; QI, HI, and SI have issue latency 12, 21, and 37, respectively.
252 (and (eq_attr "mode" "QI")
259 (and (eq_attr "mode" "QI")
266 (and (eq_attr "mode" "HI")
273 (and (eq_attr "mode" "HI")
280 (and (eq_attr "mode" "SI")
287 (and (eq_attr "mode" "SI")
362 (and (eq_attr "mode" "XF")
376 (and (eq_attr "mode" "XF")
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| H A D | k6.md | 81 (and (eq_attr "cpu" "k6")
87 (and (eq_attr "cpu" "k6")
93 (and (eq_attr "cpu" "k6")
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131 (and (eq_attr "cpu" "k6")
137 (and (eq_attr "cpu" "k6")
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| H A D | pentium.md | 49 (and (eq_attr "type" "ishift")
52 (and (eq_attr "type" "rotate")
55 (and (eq_attr "type" "ishift1")
58 (and (eq_attr "type" "rotate1")
61 (and (eq_attr "type" "call")
64 (and (eq_attr "type" "callv")
135 (and (eq_attr "cpu" "pentium")
140 (and (eq_attr "cpu" "pentium")
149 (and (eq_attr "cpu" "pentium")
179 ;; Push and pop instructions have 1 cycle latency and special
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| H A D | geode.md | 41 ;; using memory and registers.
48 (and (eq_attr "cpu" "geode")
53 (and (eq_attr "cpu" "geode")
58 (and (eq_attr "cpu" "geode")
63 (and (eq_attr "cpu" "geode")
69 (and (eq_attr "cpu" "geode")
74 (and (eq_attr "cpu" "geode")
79 (and (eq_attr "cpu" "geode")
84 (and (eq_attr "cpu" "geode")
89 (and (eq_attr "cpu" "geode")
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| /dragonfly/contrib/gcc-4.7/gcc/doc/ |
| H A D | contrib.texi | 22 and iterators.
99 Eric Botcazou for fixing middle- and backend bugs left and right.
155 and the PicoJava processor, and for GCJ config fixes.
223 various bug fixes, and the M32C, MeP, and RL78 ports.
291 and SPARC work.
587 improvements, and string clean up and testsuites.
715 clean-ups and porting work, and maintaining the IRIX, Solaris 2, and
762 hacking and developing and maintaining the Epiphany port.
823 GCC 2.95.3, and work on the Blackfin and C6X ports.
958 Daniel Towner and Hariharan Sandanagobalane contributed and
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| H A D | passes.texi | 11 @cindex passes and files of the compiler
12 @cindex files and passes of the compiler
13 @cindex compiler passes and files
149 and @file{tree-pass.h}.
288 and is defined by @code{pass_early_warn_uninitialized} and
483 A related pass that works on memory loads and stores, and not just
611 includes loop interchange, scaling, skewing and reversal and they are
686 and @file{emit-rtl.c}.
714 and @file{jump.c}.
755 generic loop analysis and manipulation code. Initialization and finalization
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| /dragonfly/share/zoneinfo/ |
| H A D | NEWS | 81 Kumar and P Chan.)
176 standard time in 1911, not 1915; and corrections to 1975 and
472 Changes to past and future time zone abbreviations and DST flags
845 negative DST during Ramadan in main and vanguard formats, and in
1293 documented before 2018a and ICU and OpenJDK do not currently
1944 unnecessary mkdir and stat system calls, and uses shorter file
1990 (thanks to Meno Hochschild) and ThreeTen-Extra, and its
2519 Iceland observed DST in 1919 and 1921, and its 1939 fallback
2886 from Asia/Yakutsk, and also with two hours subtracted) and
2930 +06 and not +08. (Thanks to Luther Ma and to Alois Treindl;
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