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Searched refs:crtc_state (Results 1 – 25 of 43) sorted by relevance

12

/dragonfly/sys/dev/drm/i915/
H A Dintel_atomic.c111 struct drm_crtc_state *crtc_state; in intel_digital_connector_atomic_check() local
126 crtc_state->mode_changed = true; in intel_digital_connector_atomic_check()
167 crtc_state = kmemdup(crtc->state, sizeof(*crtc_state), GFP_KERNEL); in intel_crtc_duplicate_state()
168 if (!crtc_state) in intel_crtc_duplicate_state()
173 crtc_state->update_pipe = false; in intel_crtc_duplicate_state()
175 crtc_state->disable_cxsr = false; in intel_crtc_duplicate_state()
178 crtc_state->fb_changed = false; in intel_crtc_duplicate_state()
179 crtc_state->fifo_changed = false; in intel_crtc_duplicate_state()
181 crtc_state->fb_bits = 0; in intel_crtc_duplicate_state()
183 return &crtc_state->base; in intel_crtc_duplicate_state()
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H A Dintel_hdmi.c142 const struct intel_crtc_state *crtc_state, in g4x_write_infoframe() argument
197 const struct intel_crtc_state *crtc_state, in ibx_write_infoframe() argument
467 &crtc_state->base.adjusted_mode; in intel_hdmi_set_avi_infoframe()
481 if (crtc_state->ycbcr420) in intel_hdmi_set_avi_infoframe()
487 crtc_state->limited_color_range ? in intel_hdmi_set_avi_infoframe()
522 &crtc_state->base.adjusted_mode); in intel_hdmi_set_hdmi_infoframe()
671 &crtc_state->base.adjusted_mode)) in intel_hdmi_set_gcp_infoframe()
897 if (crtc_state->pipe_bpp > 24) in intel_hdmi_prepare()
902 if (crtc_state->has_hdmi_sink) in intel_hdmi_prepare()
1331 to_i915(crtc_state->base.crtc->dev); in hdmi_12bpc_possible()
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H A Dintel_color.c137 struct drm_crtc *crtc = crtc_state->crtc; in i9xx_load_csc_matrix()
147 } else if (crtc_state->ctm) { in i9xx_load_csc_matrix()
352 i9xx_load_luts_internal(crtc_state->crtc, crtc_state->gamma_lut, in i9xx_load_luts()
353 to_intel_crtc_state(crtc_state)); in i9xx_load_luts()
359 struct drm_crtc *crtc = crtc_state->crtc; in haswell_load_luts()
364 to_intel_crtc_state(crtc_state); in haswell_load_luts()
380 i9xx_load_luts(crtc_state); in haswell_load_luts()
610 dev_priv->display.load_luts(crtc_state); in intel_color_load_luts()
614 struct drm_crtc_state *crtc_state) in intel_color_check() argument
628 if ((!crtc_state->degamma_lut || in intel_color_check()
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H A Dintel_atomic_plane.c111 struct intel_crtc_state *crtc_state, in intel_plane_atomic_check_with_state() argument
120 &crtc_state->base.adjusted_mode; in intel_plane_atomic_check_with_state()
136 crtc_state->base.enable ? crtc_state->pipe_src_w : 0; in intel_plane_atomic_check_with_state()
138 crtc_state->base.enable ? crtc_state->pipe_src_h : 0; in intel_plane_atomic_check_with_state()
176 ret = intel_plane->check_plane(intel_plane, crtc_state, intel_state); in intel_plane_atomic_check_with_state()
184 if (state->fb && INTEL_GEN(dev_priv) >= 9 && crtc_state->base.enable && in intel_plane_atomic_check_with_state()
195 crtc_state->active_planes |= BIT(intel_plane->id); in intel_plane_atomic_check_with_state()
197 crtc_state->active_planes &= ~BIT(intel_plane->id); in intel_plane_atomic_check_with_state()
200 &crtc_state->base, in intel_plane_atomic_check_with_state()
H A Dintel_dpll_mgr.c262 if (memcmp(&crtc_state->dpll_hw_state, in intel_find_shared_dpll()
298 crtc_state->dpll_hw_state; in intel_reference_shared_dpll()
300 crtc_state->shared_dpll = pll; in intel_reference_shared_dpll()
765 crtc_state->dpll_hw_state.wrpll = val; in hsw_ddi_hdmi_get_dpll()
811 int clock = crtc_state->port_clock; in hsw_get_dpll()
813 memset(&crtc_state->dpll_hw_state, 0, in hsw_get_dpll()
828 crtc_state->dpll_hw_state.spll = in hsw_get_dpll()
1315 memset(&crtc_state->dpll_hw_state, 0, in skl_ddi_hdmi_pll_dividers()
1366 int clock = crtc_state->port_clock; in skl_get_dpll()
1806 struct intel_crtc_state *crtc_state, in bxt_get_dpll() argument
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H A Dintel_ddi.c1105 state = crtc_state->base.state; in intel_ddi_get_crtc_new_encoder()
1516 switch (crtc_state->pipe_bpp) { in intel_ddi_set_pipe_settings()
1566 switch (crtc_state->pipe_bpp) { in intel_ddi_enable_transcoder_func()
1615 if (crtc_state->has_hdmi_sink) in intel_ddi_enable_transcoder_func()
1620 if (crtc_state->hdmi_scrambling) in intel_ddi_enable_transcoder_func()
2195 crtc_state->lane_count, is_mst); in intel_ddi_pre_enable_dp()
2244 crtc_state->has_infoframe, in intel_ddi_pre_enable_hdmi()
2245 crtc_state, conn_state); in intel_ddi_pre_enable_hdmi()
2400 if (crtc_state->has_audio) in intel_enable_ddi_dp()
2415 crtc_state->hdmi_scrambling); in intel_enable_ddi_hdmi()
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H A Dintel_drv.h867 struct intel_crtc_state *crtc_state,
1378 return crtc_state->output_types & in intel_crtc_has_dp_encoder()
1646 struct intel_crtc_state *crtc_state,
1956 struct drm_crtc_state *crtc_state; in intel_atomic_get_crtc_state() local
1958 if (IS_ERR(crtc_state)) in intel_atomic_get_crtc_state()
1959 return ERR_CAST(crtc_state); in intel_atomic_get_crtc_state()
1961 return to_intel_crtc_state(crtc_state); in intel_atomic_get_crtc_state()
1968 struct drm_crtc_state *crtc_state; in intel_atomic_get_existing_crtc_state() local
1972 if (crtc_state) in intel_atomic_get_existing_crtc_state()
1973 return to_intel_crtc_state(crtc_state); in intel_atomic_get_existing_crtc_state()
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H A Dintel_display.c5989 I915_STATE_WARN(crtc_state && crtc_state->active, in intel_connector_verify_state()
6058 if (crtc_state->base.enable && crtc_state->has_pch_encoder) in pipe_required_fdi_lanes()
9929 crtc_state->base.active = crtc_state->base.enable = true; in intel_get_load_detect_pipe()
10186 crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL); in intel_encoder_current_mode()
10834 sizeof(*crtc_state) - sizeof(crtc_state->base)); in clear_intel_crtc_state()
11820 if (!crtc_state->active || !needs_modeset(crtc_state)) in haswell_mode_set_planes_workaround()
11897 if (!crtc_state->active || needs_modeset(crtc_state)) in intel_modeset_all_pipes()
13043 if (!crtc_state->active || needs_modeset(crtc_state) || in intel_legacy_cursor_update()
13411 crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL); in intel_crtc_init()
14936 memset(crtc_state, 0, sizeof(*crtc_state)); in intel_modeset_readout_hw_state()
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H A Dintel_psr.c79 const struct intel_crtc_state *crtc_state) in vlv_psr_setup_vsc() argument
93 const struct intel_crtc_state *crtc_state) in hsw_psr_setup_vsc() argument
204 const struct intel_crtc_state *crtc_state) in vlv_psr_enable_source() argument
353 struct intel_crtc_state *crtc_state) in intel_psr_compute_config() argument
358 &crtc_state->base.adjusted_mode; in intel_psr_compute_config()
423 crtc_state->has_psr = true; in intel_psr_compute_config()
443 crtc_state->has_psr = true; in intel_psr_compute_config()
444 crtc_state->has_psr2 = true; in intel_psr_compute_config()
465 const struct intel_crtc_state *crtc_state) in hsw_psr_enable_source() argument
514 if (!crtc_state->has_psr) in intel_psr_enable()
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H A Dintel_pm.c811 if (!crtc_state->base.active) in intel_wm_plane_visible()
1413 !crtc_state->disable_cxsr; in g4x_compute_intermediate_wm()
1415 !crtc_state->disable_cxsr; in g4x_compute_intermediate_wm()
1609 width = crtc_state->pipe_src_w; in vlv_compute_wm_level()
1805 &crtc_state->wm.vlv.raw[level]; in vlv_raw_plane_wm_is_valid()
1807 &crtc_state->wm.vlv.fifo_state; in vlv_raw_plane_wm_is_valid()
1936 if (!crtc_state->fifo_changed) in vlv_atomic_update_fifo()
2034 !crtc_state->disable_cxsr; in vlv_compute_intermediate_wm()
3895 if (!crtc_state->base.enable) in skl_pipe_downscale_amount()
5593 crtc_state->wm.g4x.optimal; in g4x_wm_sanitize()
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H A Dintel_sprite.c235 const struct intel_crtc_state *crtc_state, in skl_update_plane() argument
292 scaler = &crtc_state->scaler_state.scalers[scaler_id]; in skl_update_plane()
457 const struct intel_crtc_state *crtc_state, in vlv_update_plane() argument
607 const struct intel_crtc_state *crtc_state, in ivb_update_plane() argument
763 const struct intel_crtc_state *crtc_state, in g4x_update_plane() argument
860 struct intel_crtc_state *crtc_state, in intel_check_sprite_plane() argument
903 max_scale = skl_max_scale(crtc, crtc_state); in intel_check_sprite_plane()
1038 state->ctl = skl_plane_ctl(crtc_state, state); in intel_check_sprite_plane()
1044 state->ctl = vlv_sprite_ctl(crtc_state, state); in intel_check_sprite_plane()
1050 state->ctl = ivb_sprite_ctl(crtc_state, state); in intel_check_sprite_plane()
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H A Dintel_fbc.c737 struct intel_crtc_state *crtc_state, in intel_fbc_update_state_cache() argument
747 cache->crtc.mode_flags = crtc_state->base.adjusted_mode.flags; in intel_fbc_update_state_cache()
749 cache->crtc.hsw_bdw_pixel_rate = crtc_state->pixel_rate; in intel_fbc_update_state_cache()
914 struct intel_crtc_state *crtc_state, in intel_fbc_pre_update() argument
933 intel_fbc_update_state_cache(crtc, crtc_state, plane_state); in intel_fbc_pre_update()
1121 struct intel_crtc_state *crtc_state, in intel_fbc_enable() argument
1135 WARN_ON(!crtc_state->enable_fbc); in intel_fbc_enable()
1141 if (!crtc_state->enable_fbc) in intel_fbc_enable()
1147 intel_fbc_update_state_cache(crtc, crtc_state, plane_state); in intel_fbc_enable()
H A Dintel_cdclk.c1777 to_i915(crtc_state->base.crtc->dev); in intel_crtc_compute_min_cdclk()
1780 if (!crtc_state->base.enable) in intel_crtc_compute_min_cdclk()
1786 if (IS_BROADWELL(dev_priv) && crtc_state->ips_enabled) in intel_crtc_compute_min_cdclk()
1794 if (intel_crtc_has_dp_encoder(crtc_state) && in intel_crtc_compute_min_cdclk()
1795 crtc_state->has_audio && in intel_crtc_compute_min_cdclk()
1796 crtc_state->port_clock >= 540000 && in intel_crtc_compute_min_cdclk()
1797 crtc_state->lane_count == 4) { in intel_crtc_compute_min_cdclk()
1810 if (crtc_state->has_audio && INTEL_GEN(dev_priv) >= 9) in intel_crtc_compute_min_cdclk()
1827 struct intel_crtc_state *crtc_state; in intel_compute_min_cdclk() local
1834 for_each_new_intel_crtc_in_state(intel_state, crtc, crtc_state, i) { in intel_compute_min_cdclk()
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H A Dintel_dp_mst.c99 struct drm_crtc_state *crtc_state; in intel_dp_mst_atomic_check() local
107 crtc_state = drm_atomic_get_new_crtc_state(state, old_crtc); in intel_dp_mst_atomic_check()
108 slots = to_intel_crtc_state(crtc_state)->dp_m_n.tu; in intel_dp_mst_atomic_check()
109 if (drm_atomic_crtc_needs_modeset(crtc_state) && slots > 0) { in intel_dp_mst_atomic_check()
120 to_intel_crtc_state(crtc_state)->dp_m_n.tu = 0; in intel_dp_mst_atomic_check()
H A Dintel_panel.c863 static void lpt_enable_backlight(const struct intel_crtc_state *crtc_state, in lpt_enable_backlight() argument
913 static void pch_enable_backlight(const struct intel_crtc_state *crtc_state, in pch_enable_backlight() argument
919 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; in pch_enable_backlight()
1033 static void vlv_enable_backlight(const struct intel_crtc_state *crtc_state, in vlv_enable_backlight() argument
1039 enum i915_pipe pipe = to_intel_crtc(crtc_state->base.crtc)->pipe; in vlv_enable_backlight()
1063 static void bxt_enable_backlight(const struct intel_crtc_state *crtc_state, in bxt_enable_backlight() argument
1069 enum i915_pipe pipe = to_intel_crtc(crtc_state->base.crtc)->pipe; in bxt_enable_backlight()
1111 static void cnp_enable_backlight(const struct intel_crtc_state *crtc_state, in cnp_enable_backlight() argument
1142 static void pwm_enable_backlight(const struct intel_crtc_state *crtc_state, in pwm_enable_backlight() argument
1158 enum i915_pipe pipe = to_intel_crtc(crtc_state->base.crtc)->pipe; in intel_panel_enable_backlight()
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/dragonfly/sys/dev/drm/amd/display/amdgpu_dm/
H A Damdgpu_dm_crc.c53 struct dc_stream_state *stream_state = crtc_state->stream; in amdgpu_dm_crtc_set_crc_source()
84 if (!crtc_state->crc_enabled && enable) in amdgpu_dm_crtc_set_crc_source()
86 else if (crtc_state->crc_enabled && !enable) in amdgpu_dm_crtc_set_crc_source()
89 crtc_state->crc_enabled = enable; in amdgpu_dm_crtc_set_crc_source()
93 crtc_state->crc_skip_count = 0; in amdgpu_dm_crtc_set_crc_source()
106 struct dm_crtc_state *crtc_state; in amdgpu_dm_crtc_handle_crc_irq() local
113 crtc_state = to_dm_crtc_state(crtc->state); in amdgpu_dm_crtc_handle_crc_irq()
114 stream_state = crtc_state->stream; in amdgpu_dm_crtc_handle_crc_irq()
117 if (!crtc_state->crc_enabled) in amdgpu_dm_crtc_handle_crc_irq()
126 if (crtc_state->crc_skip_count < 2) { in amdgpu_dm_crtc_handle_crc_irq()
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/dragonfly/sys/dev/drm/
H A Ddrm_atomic.c275 if (crtc_state) in drm_atomic_get_crtc_state()
276 return crtc_state; in drm_atomic_get_crtc_state()
283 if (!crtc_state) in drm_atomic_get_crtc_state()
290 crtc_state->state = state; in drm_atomic_get_crtc_state()
295 return crtc_state; in drm_atomic_get_crtc_state()
687 if (IS_ERR(crtc_state)) in drm_atomic_get_plane_state()
1120 if (IS_ERR(crtc_state)) in drm_atomic_get_connector_state()
1361 if (IS_ERR(crtc_state)) in drm_atomic_set_crtc_for_plane()
1467 if (IS_ERR(crtc_state)) in drm_atomic_set_crtc_for_connector()
1516 if (IS_ERR(crtc_state)) in drm_atomic_add_affected_connectors()
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H A Ddrm_atomic_helper.c77 if (WARN_ON(!crtc_state)) in drm_atomic_helper_plane_changed()
86 if (WARN_ON(!crtc_state)) in drm_atomic_helper_plane_changed()
193 crtc_state->active = false; in handle_conflicting_encoders()
224 crtc_state->encoder_mask &= in set_best_encoder()
235 crtc_state->encoder_mask |= in set_best_encoder()
504 if (!crtc_state) in mode_valid()
506 if (!crtc_state->mode_changed && !crtc_state->connectors_changed) in mode_valid()
509 mode = &crtc_state->mode; in mode_valid()
2724 if (IS_ERR(crtc_state)) in __drm_atomic_helper_set_config()
3085 if (IS_ERR(crtc_state)) in page_flip_common()
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H A Ddrm_simple_kms_helper.c94 struct drm_crtc_state *crtc_state; in drm_simple_kms_plane_atomic_check() local
98 crtc_state = drm_atomic_get_new_crtc_state(plane_state->state, in drm_simple_kms_plane_atomic_check()
100 if (!crtc_state->enable) in drm_simple_kms_plane_atomic_check()
103 clip.x2 = crtc_state->adjusted_mode.hdisplay; in drm_simple_kms_plane_atomic_check()
104 clip.y2 = crtc_state->adjusted_mode.vdisplay; in drm_simple_kms_plane_atomic_check()
119 return pipe->funcs->check(pipe, plane_state, crtc_state); in drm_simple_kms_plane_atomic_check()
H A Ddrm_crtc_helper.c1008 struct drm_crtc_state *crtc_state; in drm_helper_crtc_mode_set() local
1013 crtc_state = crtc->funcs->atomic_duplicate_state(crtc); in drm_helper_crtc_mode_set()
1021 if (!crtc_state) in drm_helper_crtc_mode_set()
1024 crtc_state->planes_changed = true; in drm_helper_crtc_mode_set()
1025 crtc_state->mode_changed = true; in drm_helper_crtc_mode_set()
1026 ret = drm_atomic_set_mode_for_crtc(crtc_state, mode); in drm_helper_crtc_mode_set()
1029 drm_mode_copy(&crtc_state->adjusted_mode, adjusted_mode); in drm_helper_crtc_mode_set()
1032 ret = crtc_funcs->atomic_check(crtc, crtc_state); in drm_helper_crtc_mode_set()
1037 swap(crtc->state, crtc_state); in drm_helper_crtc_mode_set()
1044 if (crtc_state) { in drm_helper_crtc_mode_set()
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H A Ddrm_blend.c309 struct drm_crtc_state *crtc_state) in drm_atomic_helper_crtc_normalize_zpos() argument
311 struct drm_atomic_state *state = crtc_state->state; in drm_atomic_helper_crtc_normalize_zpos()
330 drm_for_each_plane_mask(plane, dev, crtc_state->plane_mask) { in drm_atomic_helper_crtc_normalize_zpos()
352 crtc_state->zpos_changed = true; in drm_atomic_helper_crtc_normalize_zpos()
/dragonfly/sys/dev/drm/include/drm/
H A Ddrm_atomic_helper.h207 #define drm_atomic_crtc_state_for_each_plane(plane, crtc_state) \ argument
208 drm_for_each_plane_mask(plane, (crtc_state)->state->dev, (crtc_state)->plane_mask)
225 #define drm_atomic_crtc_state_for_each_plane_state(plane, plane_state, crtc_state) \ argument
226 drm_for_each_plane_mask(plane, (crtc_state)->state->dev, (crtc_state)->plane_mask) \
228 __drm_atomic_get_current_plane_state((crtc_state)->state, \
H A Ddrm_simple_kms_helper.h32 struct drm_crtc_state *crtc_state);
61 struct drm_crtc_state *crtc_state);
H A Ddrm_modeset_helper_vtables.h639 struct drm_crtc_state *crtc_state,
761 struct drm_crtc_state *crtc_state,
/dragonfly/sys/dev/drm/amd/display/dc/inc/hw/
H A Dtiming_generator.h68 enum crtc_state { enum
165 enum crtc_state state);

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