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Searched refs:dev_warn (Results 1 – 25 of 37) sorted by relevance

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/dragonfly/sys/dev/drm/radeon/
H A Devergreen_cs.c1143 dev_warn(p->dev, "bad SET_CONTEXT_REG " in evergreen_cs_handle_reg()
1155 dev_warn(p->dev, "bad SET_CONTEXT_REG " in evergreen_cs_handle_reg()
1162 dev_warn(p->dev, "bad SET_CONTEXT_REG " in evergreen_cs_handle_reg()
1214 dev_warn(p->dev, "bad SET_CONTEXT_REG " in evergreen_cs_handle_reg()
1226 dev_warn(p->dev, "bad SET_CONTEXT_REG " in evergreen_cs_handle_reg()
1238 dev_warn(p->dev, "bad SET_CONTEXT_REG " in evergreen_cs_handle_reg()
1250 dev_warn(p->dev, "bad SET_CONTEXT_REG " in evergreen_cs_handle_reg()
1273 dev_warn(p->dev, "bad SET_CONTEXT_REG " in evergreen_cs_handle_reg()
1311 dev_warn(p->dev, "bad SET_CONTEXT_REG " in evergreen_cs_handle_reg()
1710 dev_warn(p->dev, "bad SET_CONFIG_REG " in evergreen_cs_handle_reg()
[all …]
H A Dr600_cs.c483 dev_warn(p->dev, "%s FMASK_TILE_MAX too large " in r600_cs_track_validate_cb()
501 dev_warn(p->dev, "%s CMASK_BLOCK_MAX too large " in r600_cs_track_validate_cb()
682 dev_warn(p->dev, "%s:%d invalid num pipes %d\n", in r600_cs_track_validate_db()
1019 dev_warn(p->dev, "bad SET_CONTEXT_REG " in r600_cs_check_reg()
1037 dev_warn(p->dev, "bad SET_CONTEXT_REG " in r600_cs_check_reg()
1079 dev_warn(p->dev, "bad SET_CONTEXT_REG " in r600_cs_check_reg()
1276 dev_warn(p->dev, "bad SET_CONTEXT_REG " in r600_cs_check_reg()
1291 dev_warn(p->dev, "bad SET_CONTEXT_REG " in r600_cs_check_reg()
1304 dev_warn(p->dev, "bad SET_CONTEXT_REG " in r600_cs_check_reg()
1374 dev_warn(p->dev, "bad SET_CONTEXT_REG " in r600_cs_check_reg()
[all …]
H A Dradeon_device.c487 dev_warn(rdev->dev, "(%d) create WB bo failed\n", r); in radeon_wb_init()
499 dev_warn(rdev->dev, "(%d) pin WB bo failed\n", r); in radeon_wb_init()
507 dev_warn(rdev->dev, "(%d) map WB bo failed\n", r); in radeon_wb_init()
593 dev_warn(rdev->dev, "limiting VRAM to PCI aperture size\n"); in radeon_vram_location()
631 dev_warn(rdev->dev, "limiting GTT\n"); in radeon_gtt_location()
637 dev_warn(rdev->dev, "limiting GTT\n"); in radeon_gtt_location()
1154 dev_warn(rdev->dev, "gart size (%d) too small\n", in radeon_check_arguments()
1174 dev_warn(rdev->dev, "invalid AGP mode %d (valid mode: " in radeon_check_arguments()
1181 dev_warn(rdev->dev, "VM size (%d) must be a power of 2\n", in radeon_check_arguments()
1217 dev_warn(rdev->dev, "VM page table size (%d) too small\n", in radeon_check_arguments()
[all …]
H A Dr520.c142 dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n"); in r520_mc_program()
231 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", in r520_resume()
276 dev_warn(rdev->dev, in r520_init()
H A Dradeon_agp.c154 dev_warn(rdev->dev, "AGP aperture too small (%juM) " in radeon_agp_init()
268 dev_warn(rdev->dev, "radeon AGP reinit failed\n"); in radeon_agp_resume()
H A Drs400.c392 dev_warn(rdev->dev, "rs400: Wait MC idle timeout before updating MC.\n"); in rs400_mc_program()
466 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", in rs400_resume()
539 dev_warn(rdev->dev, in rs400_init()
H A Devergreen.c2850 dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); in evergreen_mc_program()
2901 dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); in evergreen_mc_program()
3903 dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); in evergreen_gpu_soft_reset()
4020 dev_warn(rdev->dev, "Wait for MC idle timed out !\n"); in evergreen_gpu_pci_config_reset()
4111 dev_warn(rdev->dev, "(%d) reserve RLC c bo failed\n", r); in sumo_rlc_fini()
4172 dev_warn(rdev->dev, "(%d) pin RLC sr bo failed\n", r); in sumo_rlc_init()
4179 dev_warn(rdev->dev, "(%d) map RLC sr bo failed\n", r); in sumo_rlc_init()
4251 dev_warn(rdev->dev, "(%d) pin RLC c bo failed\n", r); in sumo_rlc_init()
4258 dev_warn(rdev->dev, "(%d) map RLC c bo failed\n", r); in sumo_rlc_init()
5108 dev_warn(rdev->dev, "GPU reset failed !\n"); in evergreen_resume()
[all …]
H A Dr420.c314 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", in r420_resume()
404 dev_warn(rdev->dev, in r420_init()
H A Drs600.c864 dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n"); in rs600_gpu_init()
960 dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n"); in rs600_mc_program()
1043 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", in rs600_resume()
1117 dev_warn(rdev->dev, in rs600_init()
H A Drv770.c1022 dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); in rv770_mc_program()
1064 dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); in rv770_mc_program()
1605 dev_warn(rdev->dev, "limiting VRAM\n"); in r700_vram_gtt_location()
1614 dev_warn(rdev->dev, "limiting VRAM\n"); in r700_vram_gtt_location()
1621 dev_warn(rdev->dev, "limiting VRAM\n"); in r700_vram_gtt_location()
H A Drs690.c681 dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n"); in rs690_mc_program()
759 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", in rs690_resume()
834 dev_warn(rdev->dev, in rs690_init()
H A Drv515.c473 dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n"); in rv515_mc_program()
575 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", in rv515_resume()
654 dev_warn(rdev->dev, in rv515_init()
H A Dr600.c1311 dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); in r600_mc_program()
1351 dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); in r600_mc_program()
1386 dev_warn(rdev->dev, "limiting VRAM\n"); in r600_vram_gtt_location()
1395 dev_warn(rdev->dev, "limiting VRAM\n"); in r600_vram_gtt_location()
1402 dev_warn(rdev->dev, "limiting VRAM\n"); in r600_vram_gtt_location()
1708 dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); in r600_gpu_soft_reset()
1844 dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); in r600_gpu_pci_config_reset()
4066 dev_warn(rdev->dev, "IH ring buffer overflow (0x%08X, 0x%08X, 0x%08X)\n", in r600_get_ih_wptr()
H A Dcik.c4387 dev_warn(rdev->dev, "(%d) reserve MQD bo failed\n", r); in cik_cp_compute_fini()
4438 dev_warn(rdev->dev, "(%d) create HDP EOP bo failed\n", r); in cik_mec_init()
4451 dev_warn(rdev->dev, "(%d) pin HDP EOP bo failed\n", r); in cik_mec_init()
4457 dev_warn(rdev->dev, "(%d) map HDP EOP bo failed\n", r); in cik_mec_init()
4605 dev_warn(rdev->dev, "(%d) create MQD bo failed\n", r); in cik_cp_compute_resume()
4618 dev_warn(rdev->dev, "(%d) pin MQD bo failed\n", r); in cik_cp_compute_resume()
4624 dev_warn(rdev->dev, "(%d) map MQD bo failed\n", r); in cik_cp_compute_resume()
5002 dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); in cik_gpu_soft_reset()
5209 dev_warn(rdev->dev, "Wait for MC idle timed out !\n"); in cik_gpu_pci_config_reset()
5324 dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); in cik_mc_program()
[all …]
H A Dr300.c1448 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", in r300_resume()
1528 dev_warn(rdev->dev, in r300_init()
/dragonfly/sys/dev/drm/amd/amdgpu/
H A Damdgpu_gfx.c228 dev_warn(adev->dev, "(%d) failed to init kiq ring\n", r); in amdgpu_gfx_kiq_init_ring()
258 dev_warn(adev->dev, "failed to create KIQ bo (%d).\n", r); in amdgpu_gfx_kiq_init()
266 dev_warn(adev->dev, "(%d) reserve kiq eop bo failed\n", r); in amdgpu_gfx_kiq_init()
292 dev_warn(adev->dev, "failed to create ring mqd ob (%d)", r); in amdgpu_gfx_compute_mqd_sw_init()
299 dev_warn(adev->dev, "no memory to create MQD backup for ring %s\n", ring->name); in amdgpu_gfx_compute_mqd_sw_init()
310 dev_warn(adev->dev, "failed to create ring mqd ob (%d)", r); in amdgpu_gfx_compute_mqd_sw_init()
317 dev_warn(adev->dev, "no memory to create MQD backup for ring %s\n", ring->name); in amdgpu_gfx_compute_mqd_sw_init()
H A Damdgpu_device.c602 dev_warn(adev->dev, "(%d) create WB bo failed\n", r); in amdgpu_device_wb_init()
699 dev_warn(adev->dev, "limiting GART\n"); in amdgpu_device_gart_location()
705 dev_warn(adev->dev, "limiting GART\n"); in amdgpu_device_gart_location()
891 dev_warn(adev->dev, "VM page table size (%d) too small\n", in amdgpu_device_check_block_size()
912 dev_warn(adev->dev, "VM size (%d) too small, min is 1GB\n", in amdgpu_device_check_vm_size()
969 dev_warn(adev->dev, "sched jobs (%d) must be at least 4\n", in amdgpu_device_check_arguments()
973 dev_warn(adev->dev, "sched jobs (%d) must be a power of 2\n", in amdgpu_device_check_arguments()
980 dev_warn(adev->dev, "gart size (%d) too small\n", in amdgpu_device_check_arguments()
987 dev_warn(adev->dev, "gtt size (%d) too small\n", in amdgpu_device_check_arguments()
995 dev_warn(adev->dev, "valid range is between 4 and 9\n"); in amdgpu_device_check_arguments()
[all …]
H A Dgmc_v7_0.c272 dev_warn(adev->dev, "Wait for MC idle timedout !\n"); in gmc_v7_0_mc_program()
296 dev_warn(adev->dev, "Wait for MC idle timedout !\n"); in gmc_v7_0_mc_program()
545 dev_warn(adev->dev, "Disabling VM faults because of PRT request!\n"); in gmc_v7_0_set_prt()
1213 dev_warn(adev->dev, "Wait for GMC idle timed out !\n"); in gmc_v7_0_soft_reset()
H A Dgmc_v8_0.c463 dev_warn(adev->dev, "Wait for MC idle timedout !\n"); in gmc_v8_0_mc_program()
498 dev_warn(adev->dev, "Wait for MC idle timedout !\n"); in gmc_v8_0_mc_program()
772 dev_warn(adev->dev, "Disabling VM faults because of PRT request!\n"); in gmc_v8_0_set_prt()
1362 dev_warn(adev->dev, "Wait for GMC idle timed out !\n"); in gmc_v8_0_pre_soft_reset()
H A Dcz_ih.c200 dev_warn(adev->dev, "IH ring buffer overflow (0x%08X, 0x%08X, 0x%08X)\n", in cz_ih_get_wptr()
H A Diceland_ih.c200 dev_warn(adev->dev, "IH ring buffer overflow (0x%08X, 0x%08X, 0x%08X)\n", in iceland_ih_get_wptr()
H A Dtonga_ih.c211 dev_warn(adev->dev, "IH ring buffer overflow (0x%08X, 0x%08X, 0x%08X)\n", in tonga_ih_get_wptr()
H A Damdgpu_ucode.c418 dev_warn(adev->dev, "No ip firmware need to load\n"); in amdgpu_ucode_init_bo()
H A Dvega10_ih.c211 dev_warn(adev->dev, "IH ring buffer overflow (0x%08X, 0x%08X, 0x%08X)\n", in vega10_ih_get_wptr()
/dragonfly/sys/dev/drm/include/linux/
H A Ddevice.h69 #define dev_warn(dev, fmt, ...) \ macro

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