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Searched refs:dfixed_const (Results 1 – 12 of 12) sorted by relevance

/dragonfly/sys/dev/drm/radeon/
H A Drs690.c126 tmp.full = dfixed_const(4); in rs690_pm_info()
131 tmp.full = dfixed_const(5); in rs690_pm_info()
301 a.full = dfixed_const(16); in rs690_crtc_bandwidth_compute()
331 b.full = dfixed_const(2); in rs690_crtc_bandwidth_compute()
335 c.full = dfixed_const(2); in rs690_crtc_bandwidth_compute()
341 a.full = dfixed_const(1); in rs690_crtc_bandwidth_compute()
385 a.full = dfixed_const(16); in rs690_crtc_bandwidth_compute()
396 a.full = dfixed_const(10); in rs690_crtc_bandwidth_compute()
408 a.full = dfixed_const(3); in rs690_crtc_bandwidth_compute()
412 a.full = dfixed_const(2); in rs690_crtc_bandwidth_compute()
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H A Drv515.c975 a.full = dfixed_const(100); in rv515_crtc_bandwidth_compute()
985 c.full = dfixed_const(256); in rv515_crtc_bandwidth_compute()
1002 b.full = dfixed_const(1000); in rv515_crtc_bandwidth_compute()
1006 b.full = dfixed_const(2); in rv515_crtc_bandwidth_compute()
1010 c.full = dfixed_const(2); in rv515_crtc_bandwidth_compute()
1016 a.full = dfixed_const(1); in rv515_crtc_bandwidth_compute()
1056 a.full = dfixed_const(3); in rv515_crtc_bandwidth_compute()
1087 a.full = dfixed_const(16); in rv515_crtc_bandwidth_compute()
1098 a.full = dfixed_const(16); in rv515_crtc_bandwidth_compute()
1133 a.full = dfixed_const(16); in rv515_compute_mode_priority()
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H A Devergreen.c1940 a.full = dfixed_const(10); in evergreen_dram_bandwidth()
1960 a.full = dfixed_const(10); in evergreen_dram_bandwidth_for_display()
1979 a.full = dfixed_const(10); in evergreen_data_return_bandwidth()
1982 a.full = dfixed_const(32); in evergreen_data_return_bandwidth()
1999 a.full = dfixed_const(10); in evergreen_dmif_request_bandwidth()
2002 a.full = dfixed_const(32); in evergreen_dmif_request_bandwidth()
2060 a.full = dfixed_const(2); in evergreen_latency_watermark()
2061 b.full = dfixed_const(1); in evergreen_latency_watermark()
2116 a.full = dfixed_const(1); in evergreen_check_latency_hiding()
2244 a.full = dfixed_const(16); in evergreen_program_watermarks()
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H A Dsi.c2066 a.full = dfixed_const(1000); in dce6_dram_bandwidth()
2070 a.full = dfixed_const(10); in dce6_dram_bandwidth()
2090 a.full = dfixed_const(10); in dce6_dram_bandwidth_for_display()
2109 a.full = dfixed_const(10); in dce6_data_return_bandwidth()
2112 a.full = dfixed_const(32); in dce6_data_return_bandwidth()
2144 a.full = dfixed_const(10); in dce6_dmif_request_bandwidth()
2208 a.full = dfixed_const(2); in dce6_latency_watermark()
2209 b.full = dfixed_const(1); in dce6_latency_watermark()
2266 a.full = dfixed_const(1); in dce6_check_latency_hiding()
2399 a.full = dfixed_const(16); in dce6_program_watermarks()
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H A Dr100.c3275 temp_ff.full = dfixed_const(temp); in r100_bandwidth_update()
3282 temp_ff.full = dfixed_const(1000); in r100_bandwidth_update()
3289 temp_ff.full = dfixed_const(1000); in r100_bandwidth_update()
3339 trp_ff.full = dfixed_const(mem_trp); in r100_bandwidth_update()
3422 k1.full = dfixed_const(40); in r100_bandwidth_update()
3425 k1.full = dfixed_const(20); in r100_bandwidth_update()
3429 k1.full = dfixed_const(40); in r100_bandwidth_update()
3433 temp_ff.full = dfixed_const(2); in r100_bandwidth_update()
3435 temp_ff.full = dfixed_const(c); in r100_bandwidth_update()
3437 temp_ff.full = dfixed_const(4); in r100_bandwidth_update()
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H A Dcik.c8916 a.full = dfixed_const(1000); in dce8_dram_bandwidth()
8920 a.full = dfixed_const(10); in dce8_dram_bandwidth()
8945 a.full = dfixed_const(1000); in dce8_dram_bandwidth_for_display()
8949 a.full = dfixed_const(10); in dce8_dram_bandwidth_for_display()
8977 a.full = dfixed_const(10); in dce8_data_return_bandwidth()
8980 a.full = dfixed_const(32); in dce8_data_return_bandwidth()
9006 a.full = dfixed_const(32); in dce8_dmif_request_bandwidth()
9009 a.full = dfixed_const(10); in dce8_dmif_request_bandwidth()
9097 a.full = dfixed_const(2); in dce8_latency_watermark()
9098 b.full = dfixed_const(1); in dce8_latency_watermark()
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H A Dradeon_display.c1780 a.full = dfixed_const(src_v); in radeon_crtc_scaling_mode_fixup()
1781 b.full = dfixed_const(dst_v); in radeon_crtc_scaling_mode_fixup()
1783 a.full = dfixed_const(src_h); in radeon_crtc_scaling_mode_fixup()
1784 b.full = dfixed_const(dst_h); in radeon_crtc_scaling_mode_fixup()
1787 radeon_crtc->vsc.full = dfixed_const(1); in radeon_crtc_scaling_mode_fixup()
1788 radeon_crtc->hsc.full = dfixed_const(1); in radeon_crtc_scaling_mode_fixup()
H A Dradeon_device.c754 a.full = dfixed_const(100); in radeon_update_bandwidth_info()
755 rdev->pm.sclk.full = dfixed_const(sclk); in radeon_update_bandwidth_info()
757 rdev->pm.mclk.full = dfixed_const(mclk); in radeon_update_bandwidth_info()
761 a.full = dfixed_const(16); in radeon_update_bandwidth_info()
/dragonfly/sys/dev/drm/include/drm/
H A Ddrm_fixed.h35 #define dfixed_const(A) (u32)(((A) << 12))/* + ((B + 0.000122)*4096)) */ macro
40 #define dfixed_init(A) { .full = dfixed_const((A)) }
49 return dfixed_const(non_frac); in dfixed_floor()
56 if (A.full > dfixed_const(non_frac)) in dfixed_ceil()
57 return dfixed_const(non_frac + 1); in dfixed_ceil()
59 return dfixed_const(non_frac); in dfixed_ceil()
/dragonfly/sys/dev/drm/amd/amdgpu/
H A Ddce_v10_0.c713 a.full = dfixed_const(1000); in dce_v10_0_dram_bandwidth()
717 a.full = dfixed_const(10); in dce_v10_0_dram_bandwidth()
742 a.full = dfixed_const(1000); in dce_v10_0_dram_bandwidth_for_display()
746 a.full = dfixed_const(10); in dce_v10_0_dram_bandwidth_for_display()
774 a.full = dfixed_const(10); in dce_v10_0_data_return_bandwidth()
777 a.full = dfixed_const(32); in dce_v10_0_data_return_bandwidth()
803 a.full = dfixed_const(32); in dce_v10_0_dmif_request_bandwidth()
806 a.full = dfixed_const(10); in dce_v10_0_dmif_request_bandwidth()
894 a.full = dfixed_const(2); in dce_v10_0_latency_watermark()
895 b.full = dfixed_const(1); in dce_v10_0_latency_watermark()
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H A Ddce_v11_0.c739 a.full = dfixed_const(1000); in dce_v11_0_dram_bandwidth()
743 a.full = dfixed_const(10); in dce_v11_0_dram_bandwidth()
768 a.full = dfixed_const(1000); in dce_v11_0_dram_bandwidth_for_display()
772 a.full = dfixed_const(10); in dce_v11_0_dram_bandwidth_for_display()
800 a.full = dfixed_const(10); in dce_v11_0_data_return_bandwidth()
803 a.full = dfixed_const(32); in dce_v11_0_data_return_bandwidth()
829 a.full = dfixed_const(32); in dce_v11_0_dmif_request_bandwidth()
832 a.full = dfixed_const(10); in dce_v11_0_dmif_request_bandwidth()
920 a.full = dfixed_const(2); in dce_v11_0_latency_watermark()
921 b.full = dfixed_const(1); in dce_v11_0_latency_watermark()
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H A Damdgpu_display.c725 a.full = dfixed_const(src_v); in amdgpu_display_crtc_scaling_mode_fixup()
726 b.full = dfixed_const(dst_v); in amdgpu_display_crtc_scaling_mode_fixup()
728 a.full = dfixed_const(src_h); in amdgpu_display_crtc_scaling_mode_fixup()
729 b.full = dfixed_const(dst_h); in amdgpu_display_crtc_scaling_mode_fixup()
732 amdgpu_crtc->vsc.full = dfixed_const(1); in amdgpu_display_crtc_scaling_mode_fixup()
733 amdgpu_crtc->hsc.full = dfixed_const(1); in amdgpu_display_crtc_scaling_mode_fixup()