| /dragonfly/sys/dev/drm/amd/amdgpu/ |
| H A D | amdgpu_pll.c | 85 unsigned *fb_div, unsigned *ref_div) in amdgpu_pll_get_fb_ref_div() argument
95 if (*fb_div > fb_div_max) { in amdgpu_pll_get_fb_ref_div()
97 *fb_div = fb_div_max; in amdgpu_pll_get_fb_ref_div()
125 unsigned fb_div_min, fb_div_max, fb_div; in amdgpu_pll_compute() local
202 ref_div_max, &fb_div, &ref_div); in amdgpu_pll_compute()
217 &fb_div, &ref_div); in amdgpu_pll_compute()
226 if (fb_div < fb_div_min) { in amdgpu_pll_compute()
228 fb_div *= tmp; in amdgpu_pll_compute()
235 *fb_div_p = fb_div / 10; in amdgpu_pll_compute()
236 *frac_fb_div_p = fb_div % 10; in amdgpu_pll_compute()
[all …]
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| H A D | atombios_crtc.c | 583 u32 fb_div, in amdgpu_atombios_crtc_program_pll() argument
610 args.v1.usFbDiv = cpu_to_le16(fb_div); in amdgpu_atombios_crtc_program_pll()
620 args.v2.usFbDiv = cpu_to_le16(fb_div); in amdgpu_atombios_crtc_program_pll()
630 args.v3.usFbDiv = cpu_to_le16(fb_div); in amdgpu_atombios_crtc_program_pll()
647 args.v5.usFbDiv = cpu_to_le16(fb_div); in amdgpu_atombios_crtc_program_pll()
677 args.v6.usFbDiv = cpu_to_le16(fb_div); in amdgpu_atombios_crtc_program_pll()
826 u32 ref_div = 0, fb_div = 0, frac_fb_div = 0, post_div = 0; in amdgpu_atombios_crtc_set_pll() local
855 &fb_div, &frac_fb_div, &ref_div, &post_div); in amdgpu_atombios_crtc_set_pll()
862 ref_div, fb_div, frac_fb_div, post_div, in amdgpu_atombios_crtc_set_pll()
868 u32 amount = (((fb_div * 10) + frac_fb_div) * in amdgpu_atombios_crtc_set_pll()
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| H A D | amdgpu_atombios.h | 41 u32 fb_div; member
66 u32 fb_div; member
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| H A D | atombios_crtc.h | 49 u32 fb_div,
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| H A D | si_dpm.c | 2950 u32 fb_div, p_div; in si_init_smc_spll_table() local
2969 fb_div = (sclk_params.vCG_SPLL_FUNC_CNTL_3 & SPLL_FB_DIV_MASK) >> SPLL_FB_DIV_SHIFT; in si_init_smc_spll_table()
2973 fb_div &= ~0x00001FFF; in si_init_smc_spll_table()
2974 fb_div >>= 1; in si_init_smc_spll_table()
2979 if (fb_div & ~(SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT)) in si_init_smc_spll_table()
2989 …tmp = ((fb_div << SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_MAS… in si_init_smc_spll_table()
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| /dragonfly/sys/dev/drm/radeon/ |
| H A D | radeon_clocks.c | 42 fb_div = (fb_div >> RADEON_SPLL_FB_DIV_SHIFT) & RADEON_SPLL_FB_DIV_MASK; in radeon_legacy_get_engine_clock()
43 fb_div <<= 1; in radeon_legacy_get_engine_clock()
44 fb_div *= spll->reference_freq; in radeon_legacy_get_engine_clock()
52 sclk = fb_div / ref_div; in radeon_legacy_get_engine_clock()
72 fb_div = (fb_div >> RADEON_MPLL_FB_DIV_SHIFT) & RADEON_MPLL_FB_DIV_MASK; in radeon_legacy_get_memory_clock()
73 fb_div <<= 1; in radeon_legacy_get_memory_clock()
74 fb_div *= mpll->reference_freq; in radeon_legacy_get_memory_clock()
82 mclk = fb_div / ref_div; in radeon_legacy_get_memory_clock()
349 int *fb_div, int *post_div) in calc_eng_mem_clock() argument
375 *fb_div = req_clock & 0xff; in calc_eng_mem_clock()
[all …]
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| H A D | radeon_display.c | 920 unsigned *fb_div, unsigned *ref_div) in avivo_get_fb_ref_div() argument
930 if (*fb_div > fb_div_max) { in avivo_get_fb_ref_div()
932 *fb_div = fb_div_max; in avivo_get_fb_ref_div()
960 unsigned fb_div_min, fb_div_max, fb_div; in radeon_compute_pll_avivo() local
1040 ref_div_max, &fb_div, &ref_div); in radeon_compute_pll_avivo()
1055 &fb_div, &ref_div); in radeon_compute_pll_avivo()
1064 if (fb_div < fb_div_min) { in radeon_compute_pll_avivo()
1066 fb_div *= tmp; in radeon_compute_pll_avivo()
1073 *fb_div_p = fb_div / 10; in radeon_compute_pll_avivo()
1074 *frac_fb_div_p = fb_div % 10; in radeon_compute_pll_avivo()
[all …]
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| H A D | rs780_dpm.c | 87 r600_engine_clock_entry_set_feedback_divider(rdev, 0, dividers.fb_div); in rs780_initialize_dpm_power_state()
405 static void rs780_force_fbdiv(struct radeon_device *rdev, u32 fb_div) in rs780_force_fbdiv() argument
414 WREG32_P(FVTHROT_FBDIV_REG2, FORCED_FEEDBACK_DIV(fb_div), in rs780_force_fbdiv()
416 WREG32_P(FVTHROT_FBDIV_REG1, STARTING_FEEDBACK_DIV(fb_div), in rs780_force_fbdiv()
459 rs780_force_fbdiv(rdev, max_dividers.fb_div); in rs780_set_engine_clock_scaling()
461 if (max_dividers.fb_div > min_dividers.fb_div) { in rs780_set_engine_clock_scaling()
463 MIN_FEEDBACK_DIV(min_dividers.fb_div) | in rs780_set_engine_clock_scaling()
464 MAX_FEEDBACK_DIV(max_dividers.fb_div), in rs780_set_engine_clock_scaling()
1047 rs780_force_fbdiv(rdev, dividers.fb_div); in rs780_dpm_force_performance_level()
1054 rs780_force_fbdiv(rdev, dividers.fb_div); in rs780_dpm_force_performance_level()
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| H A D | radeon_uvd.c | 978 uint64_t fb_div = (uint64_t)vco_freq * fb_factor; in radeon_uvd_calc_upll_dividers() local
981 do_div(fb_div, ref_freq); in radeon_uvd_calc_upll_dividers()
984 if (fb_div > fb_mask) in radeon_uvd_calc_upll_dividers()
987 fb_div &= fb_mask; in radeon_uvd_calc_upll_dividers()
1006 *optimal_fb_div = fb_div; in radeon_uvd_calc_upll_dividers()
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| H A D | atombios_crtc.c | 827 u32 fb_div, in atombios_crtc_program_pll() argument
854 args.v1.usFbDiv = cpu_to_le16(fb_div); in atombios_crtc_program_pll()
864 args.v2.usFbDiv = cpu_to_le16(fb_div); in atombios_crtc_program_pll()
874 args.v3.usFbDiv = cpu_to_le16(fb_div); in atombios_crtc_program_pll()
891 args.v5.usFbDiv = cpu_to_le16(fb_div); in atombios_crtc_program_pll()
920 args.v6.usFbDiv = cpu_to_le16(fb_div); in atombios_crtc_program_pll()
1101 &fb_div, &frac_fb_div, &ref_div, &post_div); in atombios_crtc_set_pll()
1104 &fb_div, &frac_fb_div, &ref_div, &post_div); in atombios_crtc_set_pll()
1107 &fb_div, &frac_fb_div, &ref_div, &post_div); in atombios_crtc_set_pll()
1114 ref_div, fb_div, frac_fb_div, post_div, in atombios_crtc_set_pll()
[all …]
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| H A D | rv730_dpm.c | 160 mpll_func_cntl_3 |= MPLL_FB_DIV(dividers.fb_div); in rv730_populate_mclk_value()
174 u32 clk_v = ss.percentage * dividers.fb_div / (clk_s * 10000); in rv730_populate_mclk_value()
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| H A D | rv770.c | 46 unsigned fb_div = 0, vclk_div = 0, dclk_div = 0; in rv770_set_uvd_clocks() local
66 &fb_div, &vclk_div, &dclk_div); in rv770_set_uvd_clocks()
70 fb_div |= 1; in rv770_set_uvd_clocks()
100 WREG32_P(CG_UPLL_FUNC_CNTL_3, UPLL_FB_DIV(fb_div), in rv770_set_uvd_clocks()
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| H A D | radeon_legacy_crtc.c | 264 uint16_t fb_div) in radeon_compute_pll_gain() argument
271 vcoFreq = ((unsigned)ref_freq * fb_div) / ref_div; in radeon_compute_pll_gain()
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| H A D | radeon_mode.h | 599 u32 fb_div; member
624 u32 fb_div; member
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| H A D | si.c | 6994 unsigned fb_div = 0, vclk_div = 0, dclk_div = 0; in si_set_uvd_clocks() local
7012 &fb_div, &vclk_div, &dclk_div); in si_set_uvd_clocks()
7041 WREG32_P(CG_UPLL_FUNC_CNTL_3, UPLL_FB_DIV(fb_div), ~UPLL_FB_DIV_MASK); in si_set_uvd_clocks()
7046 if (fb_div < 307200) in si_set_uvd_clocks()
7487 unsigned fb_div = 0, evclk_div = 0, ecclk_div = 0; in si_set_vce_clocks() local
7508 &fb_div, &evclk_div, &ecclk_div); in si_set_vce_clocks()
7540 WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL_3, VCEPLL_FB_DIV(fb_div), ~VCEPLL_FB_DIV_MASK); in si_set_vce_clocks()
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| H A D | ni_dpm.c | 2094 u32 fb_div; in ni_init_smc_spll_table() local
2115 fb_div = (sclk_params.vCG_SPLL_FUNC_CNTL_3 & SPLL_FB_DIV_MASK) >> SPLL_FB_DIV_SHIFT; in ni_init_smc_spll_table()
2119 fb_div &= ~0x00001FFF; in ni_init_smc_spll_table()
2120 fb_div >>= 1; in ni_init_smc_spll_table()
2138 …tmp = ((fb_div << SMC_NISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT) & SMC_NISLANDS_SPLL_DIV_TABLE_FBDIV_MAS… in ni_init_smc_spll_table()
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| H A D | r600.c | 195 unsigned fb_div = 0, ref_div, vclk_div = 0, dclk_div = 0; in r600_set_uvd_clocks() local
224 &fb_div, &vclk_div, &dclk_div); in r600_set_uvd_clocks()
229 fb_div >>= 1; in r600_set_uvd_clocks()
231 fb_div |= 1; in r600_set_uvd_clocks()
247 UPLL_FB_DIV(fb_div) | in r600_set_uvd_clocks()
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| H A D | si_dpm.c | 2851 u32 fb_div, p_div; in si_init_smc_spll_table() local
2871 fb_div = (sclk_params.vCG_SPLL_FUNC_CNTL_3 & SPLL_FB_DIV_MASK) >> SPLL_FB_DIV_SHIFT; in si_init_smc_spll_table()
2875 fb_div &= ~0x00001FFF; in si_init_smc_spll_table()
2876 fb_div >>= 1; in si_init_smc_spll_table()
2881 if (fb_div & ~(SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT)) in si_init_smc_spll_table()
2891 …tmp = ((fb_div << SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_MAS… in si_init_smc_spll_table()
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| H A D | rv6xx_dpm.c | 530 return ref_clock * ((dividers->fb_div & ~1) << fb_divider_scale) / in rv6xx_calculate_vco_frequency()
608 rv6xx_memory_clock_entry_set_feedback_divider(rdev, entry, dividers.fb_div); in rv6xx_program_mclk_stepping_entry()
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| H A D | evergreen.c | 1177 unsigned fb_div = 0, vclk_div = 0, dclk_div = 0; in evergreen_set_uvd_clocks() local
1196 &fb_div, &vclk_div, &dclk_div); in evergreen_set_uvd_clocks()
1223 WREG32_P(CG_UPLL_FUNC_CNTL_3, UPLL_FB_DIV(fb_div), ~UPLL_FB_DIV_MASK); in evergreen_set_uvd_clocks()
1228 if (fb_div < 307200) in evergreen_set_uvd_clocks()
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| H A D | radeon_atombios.c | 2841 dividers->fb_div = args.v1.ucFbDiv; in radeon_atom_get_clock_dividers()
2855 dividers->fb_div = le16_to_cpu(args.v2.usFbDiv); in radeon_atom_get_clock_dividers()
2862 dividers->enable_post_div = (dividers->fb_div & 1) ? true : false; in radeon_atom_get_clock_dividers()
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| H A D | ci_dpm.c | 3215 fbdiv = dividers.fb_div & 0x3FFFFFF; in ci_calculate_sclk_params()
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| /dragonfly/sys/dev/drm/amd/display/dc/dce/ |
| H A D | dce_clock_source.c | 714 struct fixed31_32 fb_div; in calculate_ss() local
734 fb_div = dc_fixpt_from_fraction( in calculate_ss()
736 fb_div = dc_fixpt_add_int(fb_div, pll_settings->feedback_divider); in calculate_ss()
742 fb_div, dc_fixpt_from_fraction(ss_data->percentage, in calculate_ss()
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