| /dragonfly/sys/dev/drm/amd/powerplay/inc/ |
| H A D | power_state.h | 91 unsigned int lanes; member
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| /dragonfly/sys/dev/drm/i915/ |
| H A D | intel_bios.c | 581 switch (edp_link_params->lanes) { in parse_edp()
583 dev_priv->vbt.edp.lanes = 1; in parse_edp()
586 dev_priv->vbt.edp.lanes = 2; in parse_edp()
589 dev_priv->vbt.edp.lanes = 4; in parse_edp()
593 edp_link_params->lanes); in parse_edp()
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| H A D | intel_vbt_defs.h | 701 u8 lanes:4; member
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| H A D | i915_drv.h | 1748 int lanes; member
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| /dragonfly/sys/dev/drm/include/drm/ |
| H A D | drm_mipi_dsi.h | 178 unsigned int lanes; member
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| /dragonfly/sys/dev/drm/radeon/ |
| H A D | r600_dpm.h | 234 u8 r600_encode_pci_lane_width(u32 lanes);
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| H A D | rv770.c | 2021 u32 link_width_cntl, lanes, speed_cntl, tmp; in rv770_pcie_gen2_enable() local
2054 lanes = (link_width_cntl & LC_LINK_WIDTH_RD_MASK) >> LC_LINK_WIDTH_RD_SHIFT; in rv770_pcie_gen2_enable()
2057 link_width_cntl |= lanes | LC_RECONFIG_NOW | in rv770_pcie_gen2_enable()
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| H A D | r600_dpm.c | 1363 u8 r600_encode_pci_lane_width(u32 lanes) in r600_encode_pci_lane_width() argument
1367 if (lanes > 16) in r600_encode_pci_lane_width()
1370 return encoded_lanes[lanes]; in r600_encode_pci_lane_width()
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| H A D | r300.c | 492 void rv370_set_pcie_lanes(struct radeon_device *rdev, int lanes) in rv370_set_pcie_lanes() argument
504 switch (lanes) { in rv370_set_pcie_lanes()
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| H A D | r600.c | 4412 void r600_set_pcie_lanes(struct radeon_device *rdev, int lanes) in r600_set_pcie_lanes() argument
4428 switch (lanes) { in r600_set_pcie_lanes()
4452 DRM_ERROR("invalid pcie lane request: %d\n", lanes); in r600_set_pcie_lanes()
4504 u32 link_width_cntl, lanes, speed_cntl, training_cntl, tmp; in r600_pcie_gen2_enable() local
4553 lanes = (link_width_cntl & LC_LINK_WIDTH_RD_MASK) >> LC_LINK_WIDTH_RD_SHIFT; in r600_pcie_gen2_enable()
4556 link_width_cntl |= lanes | LC_RECONFIG_NOW | LC_RENEGOTIATE_EN; in r600_pcie_gen2_enable()
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| H A D | radeon_asic.h | 179 extern void rv370_set_pcie_lanes(struct radeon_device *rdev, int lanes);
370 extern void r600_set_pcie_lanes(struct radeon_device *rdev, int lanes);
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| H A D | radeon.h | 1969 void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes);
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| /dragonfly/sys/dev/drm/amd/amdgpu/ |
| H A D | amdgpu_dpm.c | 975 u8 amdgpu_encode_pci_lane_width(u32 lanes) in amdgpu_encode_pci_lane_width() argument
979 if (lanes > 16) in amdgpu_encode_pci_lane_width()
982 return encoded_lanes[lanes]; in amdgpu_encode_pci_lane_width()
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| H A D | amdgpu_dpm.h | 496 u8 amdgpu_encode_pci_lane_width(u32 lanes);
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| H A D | amdgpu.h | 1159 void (*set_pcie_lanes)(struct amdgpu_device *adev, int lanes);
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| /dragonfly/sys/dev/drm/amd/powerplay/hwmgr/ |
| H A D | processpptables.c | 703 ps->pcie.lanes = ((le32_to_cpu(pnon_clock_info->ulCapsAndSettings) & in init_non_clock_fields()
707 ps->pcie.lanes = 0; in init_non_clock_fields()
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| H A D | smu7_hwmgr.c | 3154 power_state->pcie.lanes = 0; in smu7_get_pp_table_entry_callback_func_v1()
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| /dragonfly/contrib/gcc-4.7/gcc/config/i386/ |
| H A D | sse.md | 3296 ;; Recall that the 256-bit unpck insns only shuffle within their lanes.
3364 ;; Recall that the 256-bit unpck insns only shuffle within their lanes.
4231 ;; Recall that the 256-bit unpck insns only shuffle within their lanes.
4311 ;; Recall that the 256-bit unpck insns only shuffle within their lanes.
11942 /* Shuffle the lane we care about into both lanes of the dest. */
12065 ;; Note that bits 7 and 3 of the imm8 allow lanes to be zeroed, which
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| /dragonfly/contrib/gcc-4.7/gcc/doc/ |
| H A D | arm-neon-intrinsics.texi | 4691 @subsubsection Get lanes from a vector
4825 @subsubsection Set lanes in a vector
5018 @subsubsection Set all lanes to the same value
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| /dragonfly/share/misc/ |
| H A D | pci_vendors | 14418 # 32-lanes 24-ports Gen.2
14420 # 32-lanes 24-ports Gen.2
22570 0016 SIS1100e with 4 lanes
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| /dragonfly/games/fortune/datfiles/ |
| H A D | fortunes | 24994 "Learning to change lanes takes time and patience. The best
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