/dragonfly/sys/dev/drm/amd/amdgpu/ |
H A D | sdma_v2_4.c | 308 amdgpu_ring_write(ring, lower_32_bits(addr)); in sdma_v2_4_ring_emit_fence() 310 amdgpu_ring_write(ring, lower_32_bits(seq)); in sdma_v2_4_ring_emit_fence() 316 amdgpu_ring_write(ring, lower_32_bits(addr)); in sdma_v2_4_ring_emit_fence() 613 amdgpu_ring_write(ring, lower_32_bits(gpu_addr)); in sdma_v2_4_ring_test_ring() 674 ib.ptr[1] = lower_32_bits(gpu_addr); in sdma_v2_4_ring_test_ib() 733 ib->ptr[ib->length_dw++] = lower_32_bits(src); in sdma_v2_4_vm_copy_pte() 735 ib->ptr[ib->length_dw++] = lower_32_bits(pe); in sdma_v2_4_vm_copy_pte() 762 ib->ptr[ib->length_dw++] = lower_32_bits(value); in sdma_v2_4_vm_write_pte() 1259 ib->ptr[ib->length_dw++] = lower_32_bits(src_offset); in sdma_v2_4_emit_copy_buffer() 1261 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); in sdma_v2_4_emit_copy_buffer() [all …]
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H A D | vcn_v1_0.c | 290 lower_32_bits(adev->vcn.gpu_addr)); in vcn_v1_0_mc_resume() 751 lower_32_bits(ring->gpu_addr)); in vcn_v1_0_start() 760 lower_32_bits(ring->wptr)); in vcn_v1_0_start() 1045 data1 = lower_32_bits(pd_addr); in vcn_v1_0_dec_ring_emit_vm_flush() 1113 lower_32_bits(ring->wptr)); in vcn_v1_0_enc_ring_set_wptr() 1116 lower_32_bits(ring->wptr)); in vcn_v1_0_enc_ring_set_wptr() 1181 lower_32_bits(pd_addr), 0xffffffff); in vcn_v1_0_enc_ring_emit_vm_flush() 1298 amdgpu_ring_write(ring, lower_32_bits(addr)); in vcn_v1_0_jpeg_ring_emit_fence() 1322 amdgpu_ring_write(ring, lower_32_bits(addr)); in vcn_v1_0_jpeg_ring_emit_fence() 1440 data1 = lower_32_bits(pd_addr); in vcn_v1_0_jpeg_ring_emit_vm_flush() [all …]
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H A D | sdma_v3_0.c | 390 WRITE_ONCE(*wb, (lower_32_bits(ring->wptr) << 2)); in sdma_v3_0_ring_set_wptr() 483 amdgpu_ring_write(ring, lower_32_bits(addr)); in sdma_v3_0_ring_emit_fence() 485 amdgpu_ring_write(ring, lower_32_bits(seq)); in sdma_v3_0_ring_emit_fence() 491 amdgpu_ring_write(ring, lower_32_bits(addr)); in sdma_v3_0_ring_emit_fence() 714 lower_32_bits(wptr_gpu_addr)); in sdma_v3_0_gfx_resume() 886 amdgpu_ring_write(ring, lower_32_bits(gpu_addr)); in sdma_v3_0_ring_test_ring() 947 ib.ptr[1] = lower_32_bits(gpu_addr); in sdma_v3_0_ring_test_ib() 1005 ib->ptr[ib->length_dw++] = lower_32_bits(src); in sdma_v3_0_vm_copy_pte() 1007 ib->ptr[ib->length_dw++] = lower_32_bits(pe); in sdma_v3_0_vm_copy_pte() 1030 ib->ptr[ib->length_dw++] = lower_32_bits(pe); in sdma_v3_0_vm_write_pte() [all …]
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H A D | sdma_v4_0.c | 340 lower_32_bits(ring->wptr << 2), in sdma_v4_0_ring_set_wptr() 352 lower_32_bits(ring->wptr << 2), in sdma_v4_0_ring_set_wptr() 466 amdgpu_ring_write(ring, lower_32_bits(addr)); in sdma_v4_0_ring_emit_fence() 468 amdgpu_ring_write(ring, lower_32_bits(seq)); in sdma_v4_0_ring_emit_fence() 476 amdgpu_ring_write(ring, lower_32_bits(addr)); in sdma_v4_0_ring_emit_fence() 709 lower_32_bits(wptr_gpu_addr)); in sdma_v4_0_gfx_resume() 949 amdgpu_ring_write(ring, lower_32_bits(gpu_addr)); in sdma_v4_0_ring_test_ring() 1010 ib.ptr[1] = lower_32_bits(gpu_addr); in sdma_v4_0_ring_test_ib() 1069 ib->ptr[ib->length_dw++] = lower_32_bits(src); in sdma_v4_0_vm_copy_pte() 1071 ib->ptr[ib->length_dw++] = lower_32_bits(pe); in sdma_v4_0_vm_copy_pte() [all …]
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H A D | vce_v4_0.c | 108 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr); in vce_v4_0_ring_set_wptr() 109 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr)); in vce_v4_0_ring_set_wptr() 115 lower_32_bits(ring->wptr)); in vce_v4_0_ring_set_wptr() 118 lower_32_bits(ring->wptr)); in vce_v4_0_ring_set_wptr() 121 lower_32_bits(ring->wptr)); in vce_v4_0_ring_set_wptr() 234 lower_32_bits(ring->gpu_addr)); in vce_v4_0_sriov_start() 337 WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_RPTR), lower_32_bits(ring->wptr)); in vce_v4_0_start() 338 WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_WPTR), lower_32_bits(ring->wptr)); in vce_v4_0_start() 345 WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_RPTR2), lower_32_bits(ring->wptr)); in vce_v4_0_start() 954 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr)); in vce_v4_0_ring_emit_ib() [all …]
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H A D | uvd_v7_0.c | 163 lower_32_bits(ring->wptr)); in uvd_v7_0_enc_ring_set_wptr() 166 lower_32_bits(ring->wptr)); in uvd_v7_0_enc_ring_set_wptr() 678 lower_32_bits(adev->uvd.inst[i].gpu_addr)); in uvd_v7_0_mc_resume() 689 lower_32_bits(adev->uvd.inst[i].gpu_addr + offset)); in uvd_v7_0_mc_resume() 817 lower_32_bits(adev->uvd.inst[i].gpu_addr)); in uvd_v7_0_sriov_start() 1081 lower_32_bits(ring->gpu_addr)); in uvd_v7_0_start() 1090 lower_32_bits(ring->wptr)); in uvd_v7_0_start() 1310 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr)); in uvd_v7_0_ring_emit_ib() 1332 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr)); in uvd_v7_0_enc_ring_emit_ib() 1382 data1 = lower_32_bits(pd_addr); in uvd_v7_0_ring_emit_vm_flush() [all …]
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H A D | vce_v3_0.c | 154 WREG32(mmVCE_RB_WPTR, lower_32_bits(ring->wptr)); in vce_v3_0_ring_set_wptr() 156 WREG32(mmVCE_RB_WPTR2, lower_32_bits(ring->wptr)); in vce_v3_0_ring_set_wptr() 158 WREG32(mmVCE_RB_WPTR3, lower_32_bits(ring->wptr)); in vce_v3_0_ring_set_wptr() 282 WREG32(mmVCE_RB_RPTR, lower_32_bits(ring->wptr)); in vce_v3_0_start() 283 WREG32(mmVCE_RB_WPTR, lower_32_bits(ring->wptr)); in vce_v3_0_start() 289 WREG32(mmVCE_RB_RPTR2, lower_32_bits(ring->wptr)); in vce_v3_0_start() 290 WREG32(mmVCE_RB_WPTR2, lower_32_bits(ring->wptr)); in vce_v3_0_start() 296 WREG32(mmVCE_RB_RPTR3, lower_32_bits(ring->wptr)); in vce_v3_0_start() 297 WREG32(mmVCE_RB_WPTR3, lower_32_bits(ring->wptr)); in vce_v3_0_start() 845 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr)); in vce_v3_0_ring_emit_ib() [all …]
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H A D | uvd_v6_0.c | 142 WREG32(mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr)); in uvd_v6_0_ring_set_wptr() 158 lower_32_bits(ring->wptr)); in uvd_v6_0_enc_ring_set_wptr() 161 lower_32_bits(ring->wptr)); in uvd_v6_0_enc_ring_set_wptr() 601 lower_32_bits(adev->uvd.inst->gpu_addr)); in uvd_v6_0_mc_resume() 843 lower_32_bits(ring->gpu_addr)); in uvd_v6_0_start() 857 WREG32(mmUVD_RB_RPTR, lower_32_bits(ring->wptr)); in uvd_v6_0_start() 858 WREG32(mmUVD_RB_WPTR, lower_32_bits(ring->wptr)); in uvd_v6_0_start() 864 WREG32(mmUVD_RB_RPTR2, lower_32_bits(ring->wptr)); in uvd_v6_0_start() 865 WREG32(mmUVD_RB_WPTR2, lower_32_bits(ring->wptr)); in uvd_v6_0_start() 1078 amdgpu_ring_write(ring, lower_32_bits(addr)); in uvd_v6_0_ring_emit_pipeline_sync() [all …]
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H A D | psp_v10_0.c | 157 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(fw_mem_mc_addr); in psp_v10_0_prep_cmd_buf() 203 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr); in psp_v10_0_ring_create() 304 write_frame->cmd_buf_addr_lo = lower_32_bits(cmd_buf_mc_addr); in psp_v10_0_cmd_submit() 306 write_frame->fence_addr_lo = lower_32_bits(fence_mc_addr); in psp_v10_0_cmd_submit()
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H A D | amdgpu_amdkfd_gfx_v9.c | 471 lower_32_bits(guessed_wptr)); in kgd_hqd_load() 475 lower_32_bits((uintptr_t)wptr)); in kgd_hqd_load() 575 lower_32_bits(data64)); in kgd_hqd_sdma_load() 643 low = lower_32_bits(queue_address >> 8); in kgd_hqd_is_occupied() 1034 lower_32_bits(adev->vm_manager.max_pfn - 1)); in set_vm_context_page_table_base() 1038 …G_OFFSET(MMHUB, 0, mmMMHUB_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32) + (vmid*2), lower_32_bits(base)); in set_vm_context_page_table_base() 1045 lower_32_bits(adev->vm_manager.max_pfn - 1)); in set_vm_context_page_table_base() 1049 …WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32) + (vmid*2), lower_32_bits(… in set_vm_context_page_table_base()
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H A D | uvd_v5_0.c | 87 WREG32(mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr)); in uvd_v5_0_ring_set_wptr() 262 lower_32_bits(adev->uvd.inst->gpu_addr)); in uvd_v5_0_mc_resume() 413 lower_32_bits(ring->gpu_addr)); in uvd_v5_0_start() 421 WREG32(mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr)); in uvd_v5_0_start() 542 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr)); in uvd_v5_0_ring_emit_ib()
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H A D | psp_v3_1.c | 288 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(fw_mem_mc_addr); in psp_v3_1_prep_cmd_buf() 334 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr); in psp_v3_1_ring_create() 437 write_frame->cmd_buf_addr_lo = lower_32_bits(cmd_buf_mc_addr); in psp_v3_1_cmd_submit() 439 write_frame->fence_addr_lo = lower_32_bits(fence_mc_addr); in psp_v3_1_cmd_submit()
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H A D | amdgpu_psp.c | 147 cmd->cmd.cmd_setup_tmr.buf_phy_addr_lo = lower_32_bits(tmr_mc); in psp_prep_tmr_cmd_buf() 201 cmd->cmd.cmd_load_ta.app_phy_addr_lo = lower_32_bits(asd_mc); in psp_prep_asd_cmd_buf() 205 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_lo = lower_32_bits(asd_mc_shared); in psp_prep_asd_cmd_buf()
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H A D | gfx_v9_0.c | 410 ib.ptr[2] = lower_32_bits(gpu_addr); in gfx_v9_0_ring_test_ib() 2659 amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr)); in gfx_v9_0_kiq_kcq_enable() 2661 amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr)); in gfx_v9_0_kiq_kcq_enable() 2702 lower_32_bits(ring->mqd_gpu_addr in gfx_v9_0_mqd_init() 3940 lower_32_bits(ib->gpu_addr)); in gfx_v9_0_ring_emit_ib_gfx() 3989 amdgpu_ring_write(ring, lower_32_bits(addr)); in gfx_v9_0_ring_emit_fence() 3991 amdgpu_ring_write(ring, lower_32_bits(seq)); in gfx_v9_0_ring_emit_fence() 4003 lower_32_bits(addr), upper_32_bits(addr), in gfx_v9_0_ring_emit_pipeline_sync() 4161 amdgpu_ring_write(ring, lower_32_bits(addr)); in gfx_v9_0_ring_emit_fence_kiq() 4163 amdgpu_ring_write(ring, lower_32_bits(seq)); in gfx_v9_0_ring_emit_fence_kiq() [all …]
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H A D | gfxhub_v1_0.c | 49 lower_32_bits(value)); in gfxhub_v1_0_init_gart_pt_regs() 233 lower_32_bits(adev->vm_manager.max_pfn - 1)); in gfxhub_v1_0_setup_vmid_config()
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/dragonfly/sys/dev/drm/radeon/ |
H A D | si_dma.c | 81 ib->ptr[ib->length_dw++] = lower_32_bits(pe); in si_dma_vm_copy_pages() 82 ib->ptr[ib->length_dw++] = lower_32_bits(src); in si_dma_vm_copy_pages() 264 radeon_ring_write(ring, lower_32_bits(dst_offset)); in si_copy_dma() 265 radeon_ring_write(ring, lower_32_bits(src_offset)); in si_copy_dma()
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H A D | cik_sdma.c | 206 radeon_ring_write(ring, lower_32_bits(addr)); in cik_sdma_fence_ring_emit() 612 radeon_ring_write(ring, lower_32_bits(src_offset)); in cik_copy_dma() 614 radeon_ring_write(ring, lower_32_bits(dst_offset)); in cik_copy_dma() 668 radeon_ring_write(ring, lower_32_bits(gpu_addr)); in cik_sdma_ring_test() 726 ib.ptr[1] = lower_32_bits(gpu_addr); in cik_sdma_ib_test() 815 ib->ptr[ib->length_dw++] = lower_32_bits(src); in cik_sdma_vm_copy_pages() 817 ib->ptr[ib->length_dw++] = lower_32_bits(pe); in cik_sdma_vm_copy_pages()
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H A D | r600_dma.c | 253 radeon_ring_write(ring, lower_32_bits(gpu_addr)); in r600_dma_ring_test() 295 radeon_ring_write(ring, lower_32_bits(fence->seq)); in r600_dma_fence_ring_emit() 358 ib.ptr[1] = lower_32_bits(gpu_addr); in r600_dma_ib_test()
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H A D | radeon_cursor.c | 100 lower_32_bits(radeon_crtc->cursor_addr)); in radeon_show_cursor() 116 lower_32_bits(radeon_crtc->cursor_addr)); in radeon_show_cursor()
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H A D | ni_dma.c | 327 ib->ptr[ib->length_dw++] = lower_32_bits(pe); in cayman_dma_vm_copy_pages() 328 ib->ptr[ib->length_dw++] = lower_32_bits(src); in cayman_dma_vm_copy_pages()
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/dragonfly/sys/dev/drm/amd/powerplay/smumgr/ |
H A D | smu8_smumgr.c | 207 reg_data = lower_32_bits(info.mc_addr) & in smu8_load_mec_firmware() 350 task->addr.low = lower_32_bits(smu8_smu->scratch_buffer[i].mc_addr); in smu8_smu_populate_single_scratch_task() 387 task->addr.low = lower_32_bits(smu8_smu->driver_buffer[i].mc_addr); in smu8_smu_populate_single_ucode_load_task() 620 lower_32_bits(smu8_smu->scratch_buffer[i].mc_addr)); in smu8_download_pptable_settings() 647 lower_32_bits(smu8_smu->scratch_buffer[i].mc_addr)); in smu8_upload_pptable_settings() 682 lower_32_bits(smu8_smu->toc_buffer.mc_addr)); in smu8_request_smu_load_fw()
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H A D | vega10_smumgr.c | 52 lower_32_bits(priv->smu_tables.entry[table_id].mc_addr)); in vega10_copy_table_from_smc() 83 lower_32_bits(priv->smu_tables.entry[table_id].mc_addr)); in vega10_copy_table_to_smc() 125 lower_32_bits(priv->smu_tables.entry[TOOLSTABLE].mc_addr)); in vega10_set_tools_address()
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H A D | vega12_smumgr.c | 58 lower_32_bits(priv->smu_tables.entry[table_id].mc_addr)) == 0, in vega12_copy_table_from_smc() 101 lower_32_bits(priv->smu_tables.entry[table_id].mc_addr)) == 0, in vega12_copy_table_to_smc() 193 lower_32_bits(priv->smu_tables.entry[TABLE_PMSTATUSLOG].mc_addr)); in vega12_set_tools_address()
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H A D | smu10_smumgr.c | 132 lower_32_bits(priv->smu_tables.entry[table_id].mc_addr)); in smu10_copy_table_from_smc() 164 lower_32_bits(priv->smu_tables.entry[table_id].mc_addr)); in smu10_copy_table_to_smc()
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H A D | smu7_smumgr.c | 358 entry->image_addr_low = lower_32_bits(info.mc_addr); in smu7_populate_single_firmware_entry() 402 lower_32_bits(smu_data->smu_buffer.mc_addr)); in smu7_request_smu_load_fw() 468 …smu7_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_DRV_DRAM_ADDR_LO, lower_32_bits(smu_data->hea… in smu7_request_smu_load_fw()
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