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Searched refs:mclk (Results 1 – 25 of 57) sorted by relevance

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/dragonfly/sys/dev/drm/radeon/
H A Dbtc_dpm.c2145 mclk = ps->high.mclk; in btc_apply_state_adjust_rules()
2150 mclk = ps->low.mclk; in btc_apply_state_adjust_rules()
2157 ps->low.mclk = mclk; in btc_apply_state_adjust_rules()
2175 mclk = ps->low.mclk; in btc_apply_state_adjust_rules()
2176 if (mclk < ps->medium.mclk) in btc_apply_state_adjust_rules()
2177 mclk = ps->medium.mclk; in btc_apply_state_adjust_rules()
2178 if (mclk < ps->high.mclk) in btc_apply_state_adjust_rules()
2179 mclk = ps->high.mclk; in btc_apply_state_adjust_rules()
2180 ps->low.mclk = mclk; in btc_apply_state_adjust_rules()
2182 ps->medium.mclk = mclk; in btc_apply_state_adjust_rules()
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H A Drv730_dpm.c121 LPRV7XX_SMC_MCLK_VALUE mclk) in rv730_populate_mclk_value() argument
187 mclk->mclk730.vDLL_CNTL = cpu_to_be32(dll_cntl); in rv730_populate_mclk_value()
188 mclk->mclk730.mclk_value = cpu_to_be32(memory_clock); in rv730_populate_mclk_value()
192 mclk->mclk730.vMPLL_SS = cpu_to_be32(mpll_ss); in rv730_populate_mclk_value()
193 mclk->mclk730.vMPLL_SS2 = cpu_to_be32(mpll_ss2); in rv730_populate_mclk_value()
335 table->initialState.levels[0].mclk.mclk730.vDLL_CNTL = in rv730_populate_smc_initial_state()
337 table->initialState.levels[0].mclk.mclk730.vMPLL_SS = in rv730_populate_smc_initial_state()
343 cpu_to_be32(initial_state->low.mclk); in rv730_populate_smc_initial_state()
417 state->high.mclk); in rv730_program_memory_timing_parameters()
427 state->medium.mclk); in rv730_program_memory_timing_parameters()
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H A Drv740_dpm.c189 RV7XX_SMC_MCLK_VALUE *mclk) in rv740_populate_mclk_value() argument
272 mclk->mclk770.mclk_value = cpu_to_be32(memory_clock); in rv740_populate_mclk_value()
273 mclk->mclk770.vMPLL_AD_FUNC_CNTL = cpu_to_be32(mpll_ad_func_cntl); in rv740_populate_mclk_value()
274 mclk->mclk770.vMPLL_AD_FUNC_CNTL_2 = cpu_to_be32(mpll_ad_func_cntl_2); in rv740_populate_mclk_value()
275 mclk->mclk770.vMPLL_DQ_FUNC_CNTL = cpu_to_be32(mpll_dq_func_cntl); in rv740_populate_mclk_value()
276 mclk->mclk770.vMPLL_DQ_FUNC_CNTL_2 = cpu_to_be32(mpll_dq_func_cntl_2); in rv740_populate_mclk_value()
277 mclk->mclk770.vMCLK_PWRMGT_CNTL = cpu_to_be32(mclk_pwrmgt_cntl); in rv740_populate_mclk_value()
278 mclk->mclk770.vDLL_CNTL = cpu_to_be32(dll_cntl); in rv740_populate_mclk_value()
279 mclk->mclk770.vMPLL_SS = cpu_to_be32(mpll_ss1); in rv740_populate_mclk_value()
280 mclk->mclk770.vMPLL_SS2 = cpu_to_be32(mpll_ss2); in rv740_populate_mclk_value()
[all …]
H A Drv770_dpm.c392 RV7XX_SMC_MCLK_VALUE *mclk) in rv770_populate_mclk_value() argument
658 pl->mclk, &level->mclk); in rv770_convert_power_level_to_smc()
661 pl->mclk, &level->mclk); in rv770_convert_power_level_to_smc()
664 pl->mclk, &level->mclk); in rv770_convert_power_level_to_smc()
758 state->high.mclk); in rv770_program_memory_timing_parameters()
2185 u32 sclk, mclk; in rv7xx_parse_pplib_clock_info() local
2220 pl->mclk = mclk; in rv7xx_parse_pplib_clock_info()
2265 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.mclk = pl->mclk; in rv7xx_parse_pplib_clock_info()
2539 return pl->mclk; in rv770_dpm_get_current_mclk()
2569 return requested_state->low.mclk; in rv770_dpm_get_mclk()
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H A Dcypress_dpm.c652 u32 mclk, in cypress_populate_mvdd_value() argument
726 pl->mclk, in cypress_convert_power_level_to_smc()
727 &level->mclk, in cypress_convert_power_level_to_smc()
733 pl->mclk, in cypress_convert_power_level_to_smc()
734 &level->mclk, in cypress_convert_power_level_to_smc()
835 if (pl->mclk <= in cypress_convert_mc_reg_table_entry_to_smc()
934 new_state->low.mclk)); in cypress_program_memory_timing_parameters()
937 new_state->medium.mclk)); in cypress_program_memory_timing_parameters()
940 new_state->high.mclk)); in cypress_program_memory_timing_parameters()
1050 range_table->mclk[i]; in cypress_retrieve_ac_timing_for_all_ranges()
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H A Dni_dpm.c791 u32 mclk; in ni_apply_state_adjust_rules() local
808 if (ps->performance_levels[i].mclk > max_limits->mclk) in ni_apply_state_adjust_rules()
809 ps->performance_levels[i].mclk = max_limits->mclk; in ni_apply_state_adjust_rules()
842 mclk = ps->performance_levels[0].mclk; in ni_apply_state_adjust_rules()
845 if (mclk < ps->performance_levels[i].mclk) in ni_apply_state_adjust_rules()
846 mclk = ps->performance_levels[i].mclk; in ni_apply_state_adjust_rules()
851 ps->performance_levels[i].mclk = mclk; in ni_apply_state_adjust_rules()
857 ps->performance_levels[i].mclk = ps->performance_levels[i - 1].mclk; in ni_apply_state_adjust_rules()
1321 u32 mclk, in ni_populate_mvdd_value() argument
3977 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.mclk = pl->mclk; in ni_parse_pplib_clock_info()
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H A Dsi_dpm.c3035 if (ps->performance_levels[i].mclk > max_limits->mclk) in si_apply_state_adjust_rules()
3036 ps->performance_levels[i].mclk = max_limits->mclk; in si_apply_state_adjust_rules()
3083 mclk = ps->performance_levels[0].mclk; in si_apply_state_adjust_rules()
3104 ps->performance_levels[0].mclk = mclk; in si_apply_state_adjust_rules()
3128 mclk = ps->performance_levels[0].mclk; in si_apply_state_adjust_rules()
3130 if (mclk < ps->performance_levels[i].mclk) in si_apply_state_adjust_rules()
3131 mclk = ps->performance_levels[i].mclk; in si_apply_state_adjust_rules()
3134 ps->performance_levels[i].mclk = mclk; in si_apply_state_adjust_rules()
4217 (mclk <= limits->entries[i].mclk)) in si_populate_phase_shedding_value()
5153 if (state->performance_levels[0].mclk != ulv->pl.mclk) in si_is_state_ulv_compatible()
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H A Dci_dpm.c836 u32 sclk, mclk; in ci_apply_state_adjust_rules() local
865 if (ps->performance_levels[i].mclk > max_limits->mclk) in ci_apply_state_adjust_rules()
866 ps->performance_levels[i].mclk = max_limits->mclk; in ci_apply_state_adjust_rules()
878 mclk = ps->performance_levels[0].mclk; in ci_apply_state_adjust_rules()
885 if (mclk < rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].mclk) in ci_apply_state_adjust_rules()
886 mclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].mclk; in ci_apply_state_adjust_rules()
890 ps->performance_levels[0].mclk = mclk; in ci_apply_state_adjust_rules()
2440 if (mclk < limits->entries[i].mclk) { in ci_populate_phase_value_based_on_mclk()
2558 u32 mclk, in ci_populate_memory_timing_parameters() argument
5657 rdev->pm.dpm.vce_states[i].mclk = mclk; in ci_parse_power_table()
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H A Drv770_dpm.h143 u32 mclk; member
184 LPRV7XX_SMC_MCLK_VALUE mclk);
205 RV7XX_SMC_MCLK_VALUE *mclk);
219 int rv770_populate_mvdd_value(struct radeon_device *rdev, u32 mclk,
H A Drv6xx_dpm.c457 state->high.mclk; in rv6xx_calculate_memory_clock_stepping_parameters()
459 state->high.mclk; in rv6xx_calculate_memory_clock_stepping_parameters()
461 state->medium.mclk; in rv6xx_calculate_memory_clock_stepping_parameters()
463 state->low.mclk; in rv6xx_calculate_memory_clock_stepping_parameters()
467 if (state->high.mclk == state->medium.mclk) in rv6xx_calculate_memory_clock_stepping_parameters()
474 if (state->medium.mclk == state->low.mclk) in rv6xx_calculate_memory_clock_stepping_parameters()
1822 u32 sclk, mclk; in rv6xx_parse_pplib_clock_info() local
1844 pl->mclk = mclk; in rv6xx_parse_pplib_clock_info()
2095 return pl->mclk; in rv6xx_dpm_get_current_mclk()
2125 return requested_state->low.mclk; in rv6xx_dpm_get_mclk()
[all …]
H A Dradeon_clocks.c69 uint32_t fb_div, ref_div, post_div, mclk; in radeon_legacy_get_memory_clock() local
82 mclk = fb_div / ref_div; in radeon_legacy_get_memory_clock()
86 mclk >>= 1; in radeon_legacy_get_memory_clock()
88 mclk >>= 2; in radeon_legacy_get_memory_clock()
90 mclk >>= 3; in radeon_legacy_get_memory_clock()
92 return mclk; in radeon_legacy_get_memory_clock()
H A Dradeon_atombios.c2466 u32 sclk, mclk; in radeon_atombios_parse_pplib_clock_info() local
2482 mclk = le16_to_cpu(clock_info->ci.usMemoryClockLow); in radeon_atombios_parse_pplib_clock_info()
2483 mclk |= clock_info->ci.ucMemoryClockHigh << 16; in radeon_atombios_parse_pplib_clock_info()
2484 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk; in radeon_atombios_parse_pplib_clock_info()
2491 mclk = le16_to_cpu(clock_info->si.usMemoryClockLow); in radeon_atombios_parse_pplib_clock_info()
2492 mclk |= clock_info->si.ucMemoryClockHigh << 16; in radeon_atombios_parse_pplib_clock_info()
2493 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk; in radeon_atombios_parse_pplib_clock_info()
2505 mclk |= clock_info->evergreen.ucMemoryClockHigh << 16; in radeon_atombios_parse_pplib_clock_info()
2506 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk; in radeon_atombios_parse_pplib_clock_info()
2518 mclk |= clock_info->r600.ucMemoryClockHigh << 16; in radeon_atombios_parse_pplib_clock_info()
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H A Dradeon_pm.c173 u32 sclk, mclk; in radeon_set_power_state() local
195 mclk = rdev->pm.power_state[rdev->pm.requested_power_state_index]. in radeon_set_power_state()
198 mclk = rdev->pm.power_state[rdev->pm.requested_power_state_index]. in radeon_set_power_state()
199 clock_info[rdev->pm.requested_clock_mode_index].mclk; in radeon_set_power_state()
201 if (mclk > rdev->pm.default_mclk) in radeon_set_power_state()
202 mclk = rdev->pm.default_mclk; in radeon_set_power_state()
231 if (rdev->asic->pm.set_memory_clock && (mclk != rdev->pm.current_mclk)) { in radeon_set_power_state()
233 radeon_set_memory_clock(rdev, mclk); in radeon_set_power_state()
235 rdev->pm.current_mclk = mclk; in radeon_set_power_state()
236 DRM_DEBUG_DRIVER("Setting: m: %d\n", mclk); in radeon_set_power_state()
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H A Dbtc_dpm.h43 u32 *sclk, u32 *mclk);
H A Drv6xx_dpm.h81 u32 mclk; member
H A Dcypress_dpm.h158 u8 cypress_get_strobe_mode_settings(struct radeon_device *rdev, u32 mclk);
/dragonfly/sys/dev/drm/amd/amdgpu/
H A Dsi_dpm.c3495 ps->performance_levels[i].mclk = max_limits->mclk; in si_apply_state_adjust_rules()
3542 mclk = ps->performance_levels[0].mclk; in si_apply_state_adjust_rules()
3563 ps->performance_levels[0].mclk = mclk; in si_apply_state_adjust_rules()
3587 mclk = ps->performance_levels[0].mclk; in si_apply_state_adjust_rules()
3589 if (mclk < ps->performance_levels[i].mclk) in si_apply_state_adjust_rules()
3590 mclk = ps->performance_levels[i].mclk; in si_apply_state_adjust_rules()
3593 ps->performance_levels[i].mclk = mclk; in si_apply_state_adjust_rules()
4680 (mclk <= limits->entries[i].mclk)) in si_populate_phase_shedding_value()
7296 adev->pm.dpm.vce_states[i].mclk = mclk; in si_parse_power_table()
7929 return ((si_cpl1->mclk == si_cpl2->mclk) && in si_are_power_levels_equal()
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H A Damdgpu_dpm.h93 u32 mclk; member
99 u32 mclk; member
139 u32 mclk; member
H A Dsi_dpm.h440 RV7XX_SMC_MCLK_VALUE mclk; member
600 u32 mclk; member
760 NISLANDS_SMC_MCLK_VALUE mclk; member
/dragonfly/sys/dev/drm/amd/powerplay/smumgr/
H A Diceland_smumgr.c1047 SMU71_Discrete_MemoryLevel *mclk, in iceland_calculate_mclk_params() argument
1155 mclk->MclkFrequency = memory_clock; in iceland_calculate_mclk_params()
1156 mclk->MpllFuncCntl = mpll_func_cntl; in iceland_calculate_mclk_params()
1157 mclk->MpllFuncCntl_1 = mpll_func_cntl_1; in iceland_calculate_mclk_params()
1158 mclk->MpllFuncCntl_2 = mpll_func_cntl_2; in iceland_calculate_mclk_params()
1159 mclk->MpllAdFuncCntl = mpll_ad_func_cntl; in iceland_calculate_mclk_params()
1160 mclk->MpllDqFuncCntl = mpll_dq_func_cntl; in iceland_calculate_mclk_params()
1161 mclk->MclkPwrmgtCntl = mclk_pwrmgt_cntl; in iceland_calculate_mclk_params()
1162 mclk->DllCntl = dll_cntl; in iceland_calculate_mclk_params()
1163 mclk->MpllSs1 = mpll_ss1; in iceland_calculate_mclk_params()
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H A Dci_smumgr.c1024 SMU7_Discrete_MemoryLevel *mclk, in ci_calculate_mclk_params() argument
1103 mclk->MclkFrequency = memory_clock; in ci_calculate_mclk_params()
1104 mclk->MpllFuncCntl = mpll_func_cntl; in ci_calculate_mclk_params()
1105 mclk->MpllFuncCntl_1 = mpll_func_cntl_1; in ci_calculate_mclk_params()
1106 mclk->MpllFuncCntl_2 = mpll_func_cntl_2; in ci_calculate_mclk_params()
1107 mclk->MpllAdFuncCntl = mpll_ad_func_cntl; in ci_calculate_mclk_params()
1108 mclk->MpllDqFuncCntl = mpll_dq_func_cntl; in ci_calculate_mclk_params()
1109 mclk->MclkPwrmgtCntl = mclk_pwrmgt_cntl; in ci_calculate_mclk_params()
1110 mclk->DllCntl = dll_cntl; in ci_calculate_mclk_params()
1111 mclk->MpllSs1 = mpll_ss1; in ci_calculate_mclk_params()
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H A Dtonga_smumgr.c780 SMU72_Discrete_MemoryLevel *mclk, in tonga_calculate_mclk_params() argument
896 mclk->MclkFrequency = memory_clock; in tonga_calculate_mclk_params()
897 mclk->MpllFuncCntl = mpll_func_cntl; in tonga_calculate_mclk_params()
898 mclk->MpllFuncCntl_1 = mpll_func_cntl_1; in tonga_calculate_mclk_params()
899 mclk->MpllFuncCntl_2 = mpll_func_cntl_2; in tonga_calculate_mclk_params()
900 mclk->MpllAdFuncCntl = mpll_ad_func_cntl; in tonga_calculate_mclk_params()
901 mclk->MpllDqFuncCntl = mpll_dq_func_cntl; in tonga_calculate_mclk_params()
902 mclk->MclkPwrmgtCntl = mclk_pwrmgt_cntl; in tonga_calculate_mclk_params()
903 mclk->DllCntl = dll_cntl; in tonga_calculate_mclk_params()
904 mclk->MpllSs1 = mpll_ss1; in tonga_calculate_mclk_params()
[all …]
/dragonfly/sys/dev/drm/amd/powerplay/hwmgr/
H A Dsmu7_hwmgr.c2100 table_info->max_clock_voltage_on_ac.mclk = in smu7_set_private_data_based_on_pptable_v1()
2108 hwmgr->dyn_state.max_clock_voltage_on_ac.mclk = table_info->max_clock_voltage_on_ac.mclk; in smu7_set_private_data_based_on_pptable_v1()
2892 uint32_t mclk; in smu7_apply_state_adjust_rules() local
2946 stable_pstate_mclk = max_limits->mclk; in smu7_apply_state_adjust_rules()
2968 mclk = smu7_ps->performance_levels in smu7_apply_state_adjust_rules()
2975 if (mclk < minimum_clocks.memoryClock) in smu7_apply_state_adjust_rules()
2976 mclk = (minimum_clocks.memoryClock > max_limits->mclk) ? in smu7_apply_state_adjust_rules()
3528 uint32_t sclk, mclk, activity_percent; in smu7_read_sensor() local
3546 *((uint32_t *)value) = mclk; in smu7_read_sensor()
3601 uint32_t mclk = smu7_ps->performance_levels in smu7_find_dpm_states_clocks_in_dpm_table() local
[all …]
H A Dvega10_hwmgr.c765 table_info->max_clock_voltage_on_ac.mclk = in vega10_set_private_data_based_on_pptable()
774 hwmgr->dyn_state.max_clock_voltage_on_ac.mclk = in vega10_set_private_data_based_on_pptable()
775 table_info->max_clock_voltage_on_ac.mclk; in vega10_set_private_data_based_on_pptable()
3107 uint32_t mclk; in vega10_apply_state_adjust_rules() local
3137 max_limits->mclk) in vega10_apply_state_adjust_rules()
3139 max_limits->mclk; in vega10_apply_state_adjust_rules()
3177 stable_pstate_mclk = max_limits->mclk; in vega10_apply_state_adjust_rules()
3204 if (mclk < minimum_clocks.memoryClock) in vega10_apply_state_adjust_rules()
3205 mclk = (minimum_clocks.memoryClock > max_limits->mclk) ? in vega10_apply_state_adjust_rules()
3206 max_limits->mclk : minimum_clocks.memoryClock; in vega10_apply_state_adjust_rules()
[all …]
/dragonfly/sys/dev/drm/amd/powerplay/inc/
H A Dpower_state.h171 unsigned long mclk; member

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