Searched refs:pcie_dpm_enable_mask (Results 1 – 10 of 10) sorted by relevance
168 uint32_t pcie_dpm_enable_mask; member
2609 if (data->dpm_level_enable_mask.pcie_dpm_enable_mask) { in smu7_force_dpm_highest()2611 tmp = data->dpm_level_enable_mask.pcie_dpm_enable_mask; in smu7_force_dpm_highest()2719 if (data->dpm_level_enable_mask.pcie_dpm_enable_mask) { in smu7_force_dpm_lowest()2721 data->dpm_level_enable_mask.pcie_dpm_enable_mask); in smu7_force_dpm_lowest()3857 data->dpm_level_enable_mask.pcie_dpm_enable_mask = in smu7_generate_dpm_level_enable_mask()4408 uint32_t tmp = mask & data->dpm_level_enable_mask.pcie_dpm_enable_mask; in smu7_force_clock_level()
594 data->dpm_level_enable_mask.pcie_dpm_enable_mask = in vegam_populate_smc_link_level()926 while (hw_data->dpm_level_enable_mask.pcie_dpm_enable_mask && in vegam_populate_all_graphic_levels()927 ((hw_data->dpm_level_enable_mask.pcie_dpm_enable_mask & in vegam_populate_all_graphic_levels()931 while (hw_data->dpm_level_enable_mask.pcie_dpm_enable_mask && in vegam_populate_all_graphic_levels()932 ((hw_data->dpm_level_enable_mask.pcie_dpm_enable_mask & in vegam_populate_all_graphic_levels()937 ((hw_data->dpm_level_enable_mask.pcie_dpm_enable_mask & in vegam_populate_all_graphic_levels()
861 data->dpm_level_enable_mask.pcie_dpm_enable_mask = in fiji_populate_smc_link_level()1069 while (data->dpm_level_enable_mask.pcie_dpm_enable_mask && in fiji_populate_all_graphic_levels()1070 ((data->dpm_level_enable_mask.pcie_dpm_enable_mask & in fiji_populate_all_graphic_levels()1074 while (data->dpm_level_enable_mask.pcie_dpm_enable_mask && in fiji_populate_all_graphic_levels()1075 ((data->dpm_level_enable_mask.pcie_dpm_enable_mask & in fiji_populate_all_graphic_levels()1080 ((data->dpm_level_enable_mask.pcie_dpm_enable_mask & in fiji_populate_all_graphic_levels()
790 data->dpm_level_enable_mask.pcie_dpm_enable_mask = in polaris10_populate_smc_link_level()1032 while (hw_data->dpm_level_enable_mask.pcie_dpm_enable_mask && in polaris10_populate_all_graphic_levels()1033 ((hw_data->dpm_level_enable_mask.pcie_dpm_enable_mask & in polaris10_populate_all_graphic_levels()1037 while (hw_data->dpm_level_enable_mask.pcie_dpm_enable_mask && in polaris10_populate_all_graphic_levels()1038 ((hw_data->dpm_level_enable_mask.pcie_dpm_enable_mask & in polaris10_populate_all_graphic_levels()1043 ((hw_data->dpm_level_enable_mask.pcie_dpm_enable_mask & in polaris10_populate_all_graphic_levels()
522 data->dpm_level_enable_mask.pcie_dpm_enable_mask = in tonga_populate_smc_link_level()735 if (0 == data->dpm_level_enable_mask.pcie_dpm_enable_mask) in tonga_populate_all_graphic_levels()738 while (data->dpm_level_enable_mask.pcie_dpm_enable_mask && in tonga_populate_all_graphic_levels()739 ((data->dpm_level_enable_mask.pcie_dpm_enable_mask & in tonga_populate_all_graphic_levels()744 while (data->dpm_level_enable_mask.pcie_dpm_enable_mask && in tonga_populate_all_graphic_levels()745 ((data->dpm_level_enable_mask.pcie_dpm_enable_mask & in tonga_populate_all_graphic_levels()751 ((data->dpm_level_enable_mask.pcie_dpm_enable_mask & in tonga_populate_all_graphic_levels()
789 data->dpm_level_enable_mask.pcie_dpm_enable_mask = in iceland_populate_smc_link_level()1005 while ((data->dpm_level_enable_mask.pcie_dpm_enable_mask & in iceland_populate_all_graphic_levels()1010 while ((data->dpm_level_enable_mask.pcie_dpm_enable_mask & in iceland_populate_all_graphic_levels()1016 ((data->dpm_level_enable_mask.pcie_dpm_enable_mask & in iceland_populate_all_graphic_levels()
1015 data->dpm_level_enable_mask.pcie_dpm_enable_mask = in ci_populate_smc_link_level()
112 u32 pcie_dpm_enable_mask; member
2678 pi->dpm_level_enable_mask.pcie_dpm_enable_mask = in ci_populate_smc_link_level()3877 if (pi->dpm_level_enable_mask.pcie_dpm_enable_mask) { in ci_upload_dpm_level_enable_mask()3880 pi->dpm_level_enable_mask.pcie_dpm_enable_mask); in ci_upload_dpm_level_enable_mask()4219 pi->dpm_level_enable_mask.pcie_dpm_enable_mask = in ci_generate_dpm_level_enable_mask()4246 pi->dpm_level_enable_mask.pcie_dpm_enable_mask) { in ci_dpm_force_performance_level()4248 tmp = pi->dpm_level_enable_mask.pcie_dpm_enable_mask; in ci_dpm_force_performance_level()4334 pi->dpm_level_enable_mask.pcie_dpm_enable_mask) { in ci_dpm_force_performance_level()4336 pi->dpm_level_enable_mask.pcie_dpm_enable_mask); in ci_dpm_force_performance_level()