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Searched refs:pcie_speed_table (Results 1 – 10 of 10) sorted by relevance

/dragonfly/sys/dev/drm/amd/powerplay/hwmgr/
H A Dsmu7_hwmgr.c552 phm_reset_single_dpm_table(&data->dpm_table.pcie_speed_table, in smu7_setup_default_pcie_table()
569 data->dpm_table.pcie_speed_table.count = max_entry - 1; in smu7_setup_default_pcie_table()
573 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 0, in smu7_setup_default_pcie_table()
604 data->dpm_table.pcie_speed_table.count = 6; in smu7_setup_default_pcie_table()
608 for (i = 0; i <= data->dpm_table.pcie_speed_table.count; i++) in smu7_setup_default_pcie_table()
614 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, in smu7_setup_default_pcie_table()
615 data->dpm_table.pcie_speed_table.count, in smu7_setup_default_pcie_table()
2799 *pcie_mask = data->dpm_table.pcie_speed_table.count - 1; in smu7_get_profiling_clk()
3655 dpm_table->pcie_speed_table.dpm_levels in smu7_get_maximum_link_speed()
3656 [dpm_table->pcie_speed_table.count - 1].value : in smu7_get_maximum_link_speed()
[all …]
H A Dsmu7_hwmgr.h106 struct smu7_single_dpm_table pcie_speed_table; member
/dragonfly/sys/dev/drm/amd/powerplay/smumgr/
H A Dvegam_smumgr.c579 for (i = 0; i <= dpm_table->pcie_speed_table.count; i++) { in vegam_populate_smc_link_level()
581 (uint8_t)dpm_table->pcie_speed_table.dpm_levels[i].value; in vegam_populate_smc_link_level()
583 dpm_table->pcie_speed_table.dpm_levels[i].param1); in vegam_populate_smc_link_level()
591 (uint8_t)dpm_table->pcie_speed_table.count; in vegam_populate_smc_link_level()
595 phm_get_dpm_level_enable_mask_value(&dpm_table->pcie_speed_table); in vegam_populate_smc_link_level()
872 uint8_t pcie_entry_cnt = (uint8_t) hw_data->dpm_table.pcie_speed_table.count; in vegam_populate_all_graphic_levels()
2042 PP_ASSERT_WITH_CODE(hw_data->dpm_table.pcie_speed_table.count >= 1, in vegam_init_smc_table()
2046 hw_data->dpm_table.pcie_speed_table.count; in vegam_init_smc_table()
2111 for (i = 0; i <= hw_data->dpm_table.pcie_speed_table.count; i++) { in vegam_init_smc_table()
H A Dpolaris10_smumgr.c775 for (i = 0; i <= dpm_table->pcie_speed_table.count; i++) { in polaris10_populate_smc_link_level()
777 (uint8_t)dpm_table->pcie_speed_table.dpm_levels[i].value; in polaris10_populate_smc_link_level()
779 dpm_table->pcie_speed_table.dpm_levels[i].param1); in polaris10_populate_smc_link_level()
787 (uint8_t)dpm_table->pcie_speed_table.count; in polaris10_populate_smc_link_level()
791 phm_get_dpm_level_enable_mask_value(&dpm_table->pcie_speed_table); in polaris10_populate_smc_link_level()
984 uint8_t pcie_entry_cnt = (uint8_t) hw_data->dpm_table.pcie_speed_table.count; in polaris10_populate_all_graphic_levels()
1932 for (i = 0; i <= hw_data->dpm_table.pcie_speed_table.count; i++) { in polaris10_init_smc_table()
H A Dtonga_smumgr.c505 for (i = 0; i <= dpm_table->pcie_speed_table.count; i++) { in tonga_populate_smc_link_level()
507 (uint8_t)dpm_table->pcie_speed_table.dpm_levels[i].value; in tonga_populate_smc_link_level()
509 (uint8_t)encode_pcie_lane_width(dpm_table->pcie_speed_table.dpm_levels[i].param1); in tonga_populate_smc_link_level()
521 (uint8_t)dpm_table->pcie_speed_table.count; in tonga_populate_smc_link_level()
523 phm_get_dpm_level_enable_mask_value(&dpm_table->pcie_speed_table); in tonga_populate_smc_link_level()
683 uint8_t pcie_entry_count = (uint8_t) data->dpm_table.pcie_speed_table.count; in tonga_populate_all_graphic_levels()
2336 PP_ASSERT_WITH_CODE((1 <= data->dpm_table.pcie_speed_table.count), in tonga_init_smc_table()
2340 table->PCIeBootLinkLevel = (uint8_t) (data->dpm_table.pcie_speed_table.count); in tonga_init_smc_table()
H A Dfiji_smumgr.c848 for (i = 0; i <= dpm_table->pcie_speed_table.count; i++) { in fiji_populate_smc_link_level()
850 (uint8_t)dpm_table->pcie_speed_table.dpm_levels[i].value; in fiji_populate_smc_link_level()
852 dpm_table->pcie_speed_table.dpm_levels[i].param1); in fiji_populate_smc_link_level()
860 (uint8_t)dpm_table->pcie_speed_table.count; in fiji_populate_smc_link_level()
862 phm_get_dpm_level_enable_mask_value(&dpm_table->pcie_speed_table); in fiji_populate_smc_link_level()
1022 uint8_t pcie_entry_cnt = (uint8_t) data->dpm_table.pcie_speed_table.count; in fiji_populate_all_graphic_levels()
H A Dci_smumgr.c1003 for (i = 0; i <= dpm_table->pcie_speed_table.count; i++) { in ci_populate_smc_link_level()
1005 (uint8_t)dpm_table->pcie_speed_table.dpm_levels[i].value; in ci_populate_smc_link_level()
1007 (uint8_t)encode_pcie_lane_width(dpm_table->pcie_speed_table.dpm_levels[i].param1); in ci_populate_smc_link_level()
1014 (uint8_t)dpm_table->pcie_speed_table.count; in ci_populate_smc_link_level()
1016 phm_get_dpm_level_enable_mask_value(&dpm_table->pcie_speed_table); in ci_populate_smc_link_level()
2051 PP_ASSERT_WITH_CODE((1 <= data->dpm_table.pcie_speed_table.count), in ci_init_smc_table()
2055 table->PCIeBootLinkLevel = (uint8_t)data->dpm_table.pcie_speed_table.count; in ci_init_smc_table()
H A Diceland_smumgr.c772 for (i = 0; i <= dpm_table->pcie_speed_table.count; i++) { in iceland_populate_smc_link_level()
774 (uint8_t)dpm_table->pcie_speed_table.dpm_levels[i].value; in iceland_populate_smc_link_level()
776 (uint8_t)encode_pcie_lane_width(dpm_table->pcie_speed_table.dpm_levels[i].param1); in iceland_populate_smc_link_level()
788 (uint8_t)dpm_table->pcie_speed_table.count; in iceland_populate_smc_link_level()
790 phm_get_dpm_level_enable_mask_value(&dpm_table->pcie_speed_table); in iceland_populate_smc_link_level()
/dragonfly/sys/dev/drm/radeon/
H A Dci_dpm.c2667 for (i = 0; i < dpm_table->pcie_speed_table.count; i++) { in ci_populate_smc_link_level()
2669 (u8)dpm_table->pcie_speed_table.dpm_levels[i].value; in ci_populate_smc_link_level()
3443 &pi->dpm_table.pcie_speed_table, in ci_setup_default_pcie_tables()
3447 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 0, in ci_setup_default_pcie_tables()
3451 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 0, in ci_setup_default_pcie_tables()
3454 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 1, in ci_setup_default_pcie_tables()
3457 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 2, in ci_setup_default_pcie_tables()
3460 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 3, in ci_setup_default_pcie_tables()
3463 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 4, in ci_setup_default_pcie_tables()
3466 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 5, in ci_setup_default_pcie_tables()
[all …]
H A Dci_dpm.h70 struct ci_single_dpm_table pcie_speed_table; member