/dragonfly/sys/dev/drm/i915/ |
H A D | intel_dpll_mgr.c | 150 pll->funcs.prepare(dev_priv, pll); in intel_prepare_shared_dpll() 182 pll->name, pll->active_mask, pll->on, in intel_enable_shared_dpll() 193 pll->funcs.enable(dev_priv, pll); in intel_enable_shared_dpll() 224 pll->name, pll->active_mask, pll->on, in intel_disable_shared_dpll() 235 pll->funcs.disable(dev_priv, pll); in intel_disable_shared_dpll() 439 if (!pll) in ibx_get_dpll() 770 if (!pll) in hsw_ddi_hdmi_get_dpll() 800 if (!pll) in hsw_ddi_dp_get_dpll() 837 if (!pll) in hsw_get_dpll() 927 val |= pll->state.hw_state.ctrl1 << (pll->id * 6); in skl_ddi_pll_write_ctrl1() [all …]
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H A D | intel_dpll_mgr.h | 175 struct intel_shared_dpll *pll); 184 struct intel_shared_dpll *pll); 194 struct intel_shared_dpll *pll); 204 struct intel_shared_dpll *pll, 268 struct intel_shared_dpll *pll); 270 struct intel_shared_dpll *pll,
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H A D | intel_ddi.c | 902 switch (pll->id) { in hsw_pll_to_ddi_pll_sel() 916 MISSING_CASE(pll->id); in hsw_pll_to_ddi_pll_sel() 1409 u32 val, pll; in hsw_ddi_clock_get() local 1430 if (pll == SPLL_PLL_FREQ_810MHz) in hsw_ddi_clock_get() 1432 else if (pll == SPLL_PLL_FREQ_1350MHz) in hsw_ddi_clock_get() 1434 else if (pll == SPLL_PLL_FREQ_2700MHz) in hsw_ddi_clock_get() 1454 struct intel_shared_dpll *pll; in bxt_calc_pll_link() local 1462 pll = &dev_priv->shared_dplls[pll_id]; in bxt_calc_pll_link() 1463 state = &pll->state.hw_state; in bxt_calc_pll_link() 2122 const struct intel_shared_dpll *pll) in intel_ddi_clk_select() argument [all …]
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H A D | intel_display.c | 8660 WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll, in ironlake_get_pipe_config() 9134 if (pll) { in haswell_get_ddi_port_state() 9135 WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll, in haswell_get_ddi_port_state() 11626 I915_STATE_WARN(!pll->on && pll->active_mask, in verify_single_dpll_state() 11628 I915_STATE_WARN(pll->on && !pll->active_mask, in verify_single_dpll_state() 11638 pll->active_mask, pll->state.crtc_mask); in verify_single_dpll_state() 14958 pll->on = pll->funcs.get_hw_state(dev_priv, pll, in intel_modeset_readout_hw_state() 14969 pll->active_mask = pll->state.crtc_mask; in intel_modeset_readout_hw_state() 14972 pll->name, pll->state.crtc_mask, pll->on); in intel_modeset_readout_hw_state() 15133 if (!pll->on || pll->active_mask) in intel_modeset_setup_hw_state() [all …]
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H A D | i915_reg.h | 154 #define _PLL(pll, a, b) ((a) + (pll)*((b)-(a))) argument 155 #define _MMIO_PLL(pll, a, b) _MMIO(_PLL(pll, a, b)) argument 7255 #define PCH_DPLL(pll) _MMIO(pll == 0 ? _PCH_DPLL_A : _PCH_DPLL_B) argument 7262 #define PCH_FP0(pll) _MMIO(pll == 0 ? _PCH_FPA0 : _PCH_FPB0) argument 7263 #define PCH_FP1(pll) _MMIO(pll == 0 ? _PCH_FPA1 : _PCH_FPB1) argument 8442 #define WRPLL_CTL(pll) _MMIO_PIPE(pll, _WRPLL_CTL1, _WRPLL_CTL2) argument 8466 #define PORT_CLK_SEL_WRPLL(pll) (((pll)+4)<<29) argument 8604 #define DPCLKA_CFGCR0_DDI_CLK_SEL(pll, port) ((pll) << ((port)*2)) argument 8613 #define CNL_DPLL_ENABLE(pll) _MMIO_PLL(pll, DPLL0_ENABLE, DPLL1_ENABLE) argument 8632 #define CNL_DPLL_CFGCR0(pll) _MMIO_PLL(pll, _CNL_DPLL0_CFGCR0, _CNL_DPLL1_CFGCR0) argument [all …]
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/dragonfly/sys/dev/drm/amd/amdgpu/ |
H A D | amdgpu_pll.c | 142 ref_div_min = pll->reference_div; in amdgpu_pll_compute() 144 ref_div_min = pll->min_ref_div; in amdgpu_pll_compute() 148 ref_div_max = pll->reference_div; in amdgpu_pll_compute() 150 ref_div_max = pll->max_ref_div; in amdgpu_pll_compute() 154 post_div_min = pll->post_div; in amdgpu_pll_compute() 155 post_div_max = pll->post_div; in amdgpu_pll_compute() 160 vco_min = pll->lcd_pll_out_min; in amdgpu_pll_compute() 161 vco_max = pll->lcd_pll_out_max; in amdgpu_pll_compute() 163 vco_min = pll->pll_out_min; in amdgpu_pll_compute() 164 vco_max = pll->pll_out_max; in amdgpu_pll_compute() [all …]
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H A D | atombios_crtc.c | 827 struct amdgpu_pll *pll; in amdgpu_atombios_crtc_set_pll() local 837 pll = &adev->clock.ppll[0]; in amdgpu_atombios_crtc_set_pll() 840 pll = &adev->clock.ppll[1]; in amdgpu_atombios_crtc_set_pll() 845 pll = &adev->clock.ppll[2]; in amdgpu_atombios_crtc_set_pll() 850 pll->flags = amdgpu_crtc->pll_flags; in amdgpu_atombios_crtc_set_pll() 851 pll->reference_div = amdgpu_crtc->pll_reference_div; in amdgpu_atombios_crtc_set_pll() 852 pll->post_div = amdgpu_crtc->pll_post_div; in amdgpu_atombios_crtc_set_pll() 854 amdgpu_pll_compute(pll, amdgpu_crtc->adjusted_clock, &pll_clock, in amdgpu_atombios_crtc_set_pll() 876 (125 * 25 * pll->reference_freq / 100); in amdgpu_atombios_crtc_set_pll() 879 (125 * 25 * pll->reference_freq / 100); in amdgpu_atombios_crtc_set_pll()
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H A D | amdgpu_pll.h | 27 void amdgpu_pll_compute(struct amdgpu_pll *pll,
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H A D | dce_v10_0.c | 2218 int pll; in dce_v10_0_pick_pll() local 2226 pll = amdgpu_pll_get_shared_dp_ppll(crtc); in dce_v10_0_pick_pll() 2227 if (pll != ATOM_PPLL_INVALID) in dce_v10_0_pick_pll() 2228 return pll; in dce_v10_0_pick_pll() 2232 pll = amdgpu_pll_get_shared_nondp_ppll(crtc); in dce_v10_0_pick_pll() 2233 if (pll != ATOM_PPLL_INVALID) in dce_v10_0_pick_pll() 2234 return pll; in dce_v10_0_pick_pll()
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H A D | dce_v11_0.c | 2251 int pll; in dce_v11_0_pick_pll() local 2295 pll = amdgpu_pll_get_shared_dp_ppll(crtc); in dce_v11_0_pick_pll() 2296 if (pll != ATOM_PPLL_INVALID) in dce_v11_0_pick_pll() 2297 return pll; in dce_v11_0_pick_pll() 2301 pll = amdgpu_pll_get_shared_nondp_ppll(crtc); in dce_v11_0_pick_pll() 2302 if (pll != ATOM_PPLL_INVALID) in dce_v11_0_pick_pll() 2303 return pll; in dce_v11_0_pick_pll()
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/dragonfly/sys/dev/drm/radeon/ |
H A D | radeon_display.c | 979 ref_div_min = pll->min_ref_div; in radeon_compute_pll_avivo() 988 ref_div_max = pll->max_ref_div; in radeon_compute_pll_avivo() 992 post_div_min = pll->post_div; in radeon_compute_pll_avivo() 993 post_div_max = pll->post_div; in radeon_compute_pll_avivo() 1001 vco_min = pll->pll_out_min; in radeon_compute_pll_avivo() 1002 vco_max = pll->pll_out_max; in radeon_compute_pll_avivo() 1025 den = pll->reference_freq; in radeon_compute_pll_avivo() 1127 DRM_DEBUG_KMS("PLL freq %lu %u %u\n", freq, pll->min_ref_div, pll->max_ref_div); in radeon_compute_pll_legacy() 1134 pll_out_min = pll->pll_out_min; in radeon_compute_pll_legacy() 1147 if (pll_in < pll->pll_in_min) in radeon_compute_pll_legacy() [all …]
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H A D | atombios_crtc.c | 1070 struct radeon_pll *pll; in atombios_crtc_set_pll() local 1081 pll = &rdev->clock.p1pll; in atombios_crtc_set_pll() 1084 pll = &rdev->clock.p2pll; in atombios_crtc_set_pll() 1089 pll = &rdev->clock.dcpll; in atombios_crtc_set_pll() 1867 int pll; in radeon_atom_pick_pll() local 1878 return pll; in radeon_atom_pick_pll() 1884 return pll; in radeon_atom_pick_pll() 1926 return pll; in radeon_atom_pick_pll() 1932 return pll; in radeon_atom_pick_pll() 1981 return pll; in radeon_atom_pick_pll() [all …]
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H A D | radeon_legacy_crtc.c | 754 struct radeon_pll *pll; in radeon_set_pll() local 777 pll = &rdev->clock.p2pll; in radeon_set_pll() 779 pll = &rdev->clock.p1pll; in radeon_set_pll() 781 pll->flags = RADEON_PLL_LEGACY; in radeon_set_pll() 784 pll->flags |= RADEON_PLL_PREFER_HIGH_FB_DIV; in radeon_set_pll() 786 pll->flags |= RADEON_PLL_PREFER_LOW_REF_DIV; in radeon_set_pll() 798 pll->flags |= RADEON_PLL_NO_ODD_POST_DIV; in radeon_set_pll() 813 pll->flags |= RADEON_PLL_USE_REF_DIV; in radeon_set_pll() 821 radeon_compute_pll_legacy(pll, mode->clock, in radeon_set_pll() 852 pll_gain = radeon_compute_pll_gain(pll->reference_freq, in radeon_set_pll()
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H A D | radeon_legacy_tv.c | 242 struct radeon_pll *pll; in radeon_legacy_tv_get_std_mode() local 246 pll = &rdev->clock.p2pll; in radeon_legacy_tv_get_std_mode() 248 pll = &rdev->clock.p1pll; in radeon_legacy_tv_get_std_mode() 251 *pll_ref_freq = pll->reference_freq; in radeon_legacy_tv_get_std_mode() 256 if (pll->reference_freq == 2700) in radeon_legacy_tv_get_std_mode() 261 if (pll->reference_freq == 2700) in radeon_legacy_tv_get_std_mode() 434 struct radeon_pll *pll; in radeon_legacy_tv_init_restarts() local 438 pll = &rdev->clock.p2pll; in radeon_legacy_tv_init_restarts() 440 pll = &rdev->clock.p1pll; in radeon_legacy_tv_init_restarts()
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H A D | radeon_mode.h | 821 extern void radeon_compute_pll_legacy(struct radeon_pll *pll, 829 extern void radeon_compute_pll_avivo(struct radeon_pll *pll,
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/dragonfly/sys/dev/netif/ath/ath_hal/ar9001/ |
H A D | ar9130_phy.c | 34 uint32_t pll; in ar9130InitPLL() local 40 pll = 0x1450; in ar9130InitPLL() 42 pll = 0x1458; in ar9130InitPLL() 44 OS_REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll); in ar9130InitPLL()
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H A D | ar9160_attach.c | 92 uint32_t pll = SM(0x5, AR_RTC_SOWL_PLL_REFDIV); in ar9160InitPLL() local 95 pll |= SM(0x1, AR_RTC_SOWL_PLL_CLKSEL); in ar9160InitPLL() 97 pll |= SM(0x2, AR_RTC_SOWL_PLL_CLKSEL); in ar9160InitPLL() 100 pll |= SM(0x50, AR_RTC_SOWL_PLL_DIV); in ar9160InitPLL() 102 pll |= SM(0x58, AR_RTC_SOWL_PLL_DIV); in ar9160InitPLL() 104 pll |= SM(0x58, AR_RTC_SOWL_PLL_DIV); in ar9160InitPLL() 106 OS_REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll); in ar9160InitPLL()
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/dragonfly/sys/dev/netif/ath/ath_hal/ar9002/ |
H A D | ar9280_attach.c | 107 uint32_t pll = SM(0x5, AR_RTC_SOWL_PLL_REFDIV); in ar9280InitPLL() local 116 pll = IS_5GHZ_FAST_CLOCK_EN(ah, chan) ? 0x142c : 0x2850; in ar9280InitPLL() 118 pll |= SM(0x1, AR_RTC_SOWL_PLL_CLKSEL); in ar9280InitPLL() 120 pll |= SM(0x2, AR_RTC_SOWL_PLL_CLKSEL); in ar9280InitPLL() 122 pll = SM(0x5, AR_RTC_SOWL_PLL_REFDIV); in ar9280InitPLL() 125 pll |= SM(0x1, AR_RTC_SOWL_PLL_CLKSEL); in ar9280InitPLL() 127 pll |= SM(0x2, AR_RTC_SOWL_PLL_CLKSEL); in ar9280InitPLL() 129 pll |= SM(0x28, AR_RTC_SOWL_PLL_DIV); in ar9280InitPLL() 131 pll |= SM(0x2c, AR_RTC_SOWL_PLL_DIV); in ar9280InitPLL() 133 pll |= SM(0x2c, AR_RTC_SOWL_PLL_DIV); in ar9280InitPLL() [all …]
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/dragonfly/sys/dev/netif/bwn/siba/ |
H A D | siba_core.c | 1130 uint32_t bufsth = 0, pll, pmu; in siba_cc_pmu1_pll0_init() local 1174 pll = siba_cc_pll_read(scc, SIBA_CC_PMU1_PLL0); in siba_cc_pmu1_pll0_init() 1178 siba_cc_pll_write(scc, SIBA_CC_PMU1_PLL0, pll); in siba_cc_pmu1_pll0_init() 1183 pll |= (1 << 17) & SIBA_CC_PMU1_PLL2_NDIVMODE; in siba_cc_pmu1_pll0_init() 1187 pll &= ~SIBA_CC_PMU1_PLL3_NDIVFRAC; in siba_cc_pmu1_pll0_init() 1193 pll &= ~SIBA_CC_PMU1_PLL5_CLKDRV; in siba_cc_pmu1_pll0_init() 1212 uint32_t pmu, tmp, pll; in siba_cc_pmu0_pll0_init() local 1263 pll |= SIBA_CC_PMU0_PLL0_PDIV_MSK; in siba_cc_pmu0_pll0_init() 1265 pll &= ~SIBA_CC_PMU0_PLL0_PDIV_MSK; in siba_cc_pmu0_pll0_init() 1275 pll |= SIBA_CC_PMU0_PLL1_STOPMOD; in siba_cc_pmu0_pll0_init() [all …]
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/dragonfly/sys/dev/powermng/powernow/ |
H A D | powernow.c | 103 unsigned int pll; member 119 uint8_t pll; member 189 cstate->pll = pst->pll; in k8pnow_states() 292 WRITE_FIDVID(val, cvid, (uint64_t) cstate->pll * 1000 / 5); in k8_powernow_setperf() 298 WRITE_FIDVID(fid, cvid, (uint64_t) cstate->pll * 1000 / 5); in k8_powernow_setperf()
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/dragonfly/sys/dev/crypto/hifn/ |
H A D | hifn7751.c | 300 hifn_getpllconfig(device_t dev, u_int *pll) in hifn_getpllconfig() argument 342 *pll = pllconfig; in hifn_getpllconfig() 1214 u_int32_t pll; in hifn_init_pci_registers() local 1221 pll = READ_REG_1(sc, HIFN_1_PLL); in hifn_init_pci_registers() 1222 pll = (pll &~ (HIFN_PLL_PK_CLK_SEL | HIFN_PLL_PE_CLK_SEL)) in hifn_init_pci_registers() 1224 WRITE_REG_1(sc, HIFN_1_PLL, pll); in hifn_init_pci_registers() 1227 pll = (pll &~ HIFN_PLL_CONFIG) | sc->sc_pllconfig; in hifn_init_pci_registers() 1228 WRITE_REG_1(sc, HIFN_1_PLL, pll); in hifn_init_pci_registers() 1231 pll &= ~HIFN_PLL_BP; in hifn_init_pci_registers() 1232 WRITE_REG_1(sc, HIFN_1_PLL, pll); in hifn_init_pci_registers() [all …]
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/dragonfly/sys/dev/netif/ath/ath_hal/ar5416/ |
H A D | ar5416_reset.c | 1503 uint32_t pll = AR_RTC_PLL_REFDIV_5 | AR_RTC_PLL_DIV2; in ar5416InitPLL() local 1506 pll |= SM(0x1, AR_RTC_PLL_CLKSEL); in ar5416InitPLL() 1508 pll |= SM(0x2, AR_RTC_PLL_CLKSEL); in ar5416InitPLL() 1511 pll |= SM(0xa, AR_RTC_PLL_DIV); in ar5416InitPLL() 1513 pll |= SM(0xb, AR_RTC_PLL_DIV); in ar5416InitPLL() 1515 pll |= SM(0xb, AR_RTC_PLL_DIV); in ar5416InitPLL() 1517 OS_REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll); in ar5416InitPLL()
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/dragonfly/sys/bus/cam/scsi/ |
H A D | scsi_ch.h | 290 u_int8_t pll[2]; /* parameter list length */ member
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H A D | scsi_ch.c | 1669 scsi_ulto2b(sizeof(*parameters), scsi_cmd->pll); in scsi_send_volume_tag()
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/dragonfly/sys/contrib/dev/ath/ath_hal/ar9300/ |
H A D | ar9300_reset.c | 1367 u_int32_t pll; in ar9300_init_pll() local 1607 pll = SM(0x5, AR_RTC_PLL_REFDIV); in ar9300_init_pll() 1612 pll |= SM(0x1, AR_RTC_PLL_CLKSEL); in ar9300_init_pll() 1614 pll |= SM(0x2, AR_RTC_PLL_CLKSEL); in ar9300_init_pll() 1618 pll |= SM(0x28, AR_RTC_PLL_DIV); in ar9300_init_pll() 1623 pll = 0x142c; in ar9300_init_pll() 1626 pll |= SM(0x2c, AR_RTC_PLL_DIV); in ar9300_init_pll() 1629 OS_REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll); in ar9300_init_pll()
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