| /dragonfly/sys/dev/drm/radeon/ |
| H A D | rv730_dpm.c | 42 RV770_SMC_SCLK_VALUE *sclk) in rv730_populate_sclk_value() argument
109 sclk->sclk_value = cpu_to_be32(engine_clock); in rv730_populate_sclk_value()
110 sclk->vCG_SPLL_FUNC_CNTL = cpu_to_be32(spll_func_cntl); in rv730_populate_sclk_value()
111 sclk->vCG_SPLL_FUNC_CNTL_2 = cpu_to_be32(spll_func_cntl_2); in rv730_populate_sclk_value()
309 table->ACPIState.levels[0].sclk.sclk_value = 0; in rv730_populate_smc_acpi_state()
345 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL = in rv730_populate_smc_initial_state()
356 table->initialState.levels[0].sclk.sclk_value = in rv730_populate_smc_initial_state()
357 cpu_to_be32(initial_state->low.sclk); in rv730_populate_smc_initial_state()
416 state->high.sclk, in rv730_program_memory_timing_parameters()
426 state->medium.sclk, in rv730_program_memory_timing_parameters()
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| H A D | btc_dpm.c | 2116 ps->high.sclk = max_limits->sclk; in btc_apply_state_adjust_rules()
2125 ps->medium.sclk = max_limits->sclk; in btc_apply_state_adjust_rules()
2133 if (ps->low.sclk > max_limits->sclk) in btc_apply_state_adjust_rules()
2134 ps->low.sclk = max_limits->sclk; in btc_apply_state_adjust_rules()
2144 sclk = ps->low.sclk; in btc_apply_state_adjust_rules()
2149 sclk = ps->low.sclk; in btc_apply_state_adjust_rules()
2156 ps->low.sclk = sclk; in btc_apply_state_adjust_rules()
2165 if (ps->medium.sclk < ps->low.sclk) in btc_apply_state_adjust_rules()
2166 ps->medium.sclk = ps->low.sclk; in btc_apply_state_adjust_rules()
2169 if (ps->high.sclk < ps->medium.sclk) in btc_apply_state_adjust_rules()
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| H A D | rv770_dpm.c | 284 a_n = (int)state->high.sclk * pi->lhp + (int)state->medium.sclk * in rv770_populate_smc_t()
634 &level->sclk); in rv770_convert_power_level_to_smc()
637 &level->sclk); in rv770_convert_power_level_to_smc()
640 &level->sclk); in rv770_convert_power_level_to_smc()
752 if (state->high.sclk < (state->low.sclk * 0xFF / 0x40)) in rv770_program_memory_timing_parameters()
1447 if (new_state->high.sclk >= current_state->high.sclk) in rv770_set_uvd_clock_before_set_eng_clock()
1464 if (new_state->high.sclk < current_state->high.sclk) in rv770_set_uvd_clock_after_set_eng_clock()
2185 u32 sclk, mclk; in rv7xx_parse_pplib_clock_info() local
2221 pl->sclk = sclk; in rv7xx_parse_pplib_clock_info()
2264 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk = pl->sclk; in rv7xx_parse_pplib_clock_info()
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| H A D | trinity_dpm.c | 1341 if (sclk < 20000) in trinity_calculate_vce_wm()
1371 if (sclk < min) in trinity_get_sleep_divider_id_from_clock()
1572 ps->levels[i].sclk = in trinity_apply_state_adjust_rules()
1578 if (ps->levels[i].sclk < rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].sclk) in trinity_apply_state_adjust_rules()
1579 ps->levels[i].sclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].sclk; in trinity_apply_state_adjust_rules()
1719 u32 sclk; in trinity_parse_pplib_clock_info() local
1723 pl->sclk = sclk; in trinity_parse_pplib_clock_info()
1810 u32 sclk; in trinity_parse_power_table() local
1816 rdev->pm.dpm.vce_states[i].sclk = sclk; in trinity_parse_power_table()
2027 i, pl->sclk, in trinity_dpm_print_power_state()
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| H A D | rv740_dpm.c | 122 RV770_SMC_SCLK_VALUE *sclk) in rv740_populate_sclk_value() argument
177 sclk->sclk_value = cpu_to_be32(engine_clock); in rv740_populate_sclk_value()
178 sclk->vCG_SPLL_FUNC_CNTL = cpu_to_be32(spll_func_cntl); in rv740_populate_sclk_value()
179 sclk->vCG_SPLL_FUNC_CNTL_2 = cpu_to_be32(spll_func_cntl_2); in rv740_populate_sclk_value()
180 sclk->vCG_SPLL_FUNC_CNTL_3 = cpu_to_be32(spll_func_cntl_3); in rv740_populate_sclk_value()
181 sclk->vCG_SPLL_SPREAD_SPECTRUM = cpu_to_be32(cg_spll_spread_spectrum); in rv740_populate_sclk_value()
182 sclk->vCG_SPLL_SPREAD_SPECTRUM_2 = cpu_to_be32(cg_spll_spread_spectrum_2); in rv740_populate_sclk_value()
383 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL = cpu_to_be32(spll_func_cntl); in rv740_populate_smc_acpi_state()
384 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 = cpu_to_be32(spll_func_cntl_2); in rv740_populate_smc_acpi_state()
385 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 = cpu_to_be32(spll_func_cntl_3); in rv740_populate_smc_acpi_state()
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| H A D | ni_dpm.c | 810 if (ps->performance_levels[i].sclk > max_limits->sclk) in ni_apply_state_adjust_rules()
811 ps->performance_levels[i].sclk = max_limits->sclk; in ni_apply_state_adjust_rules()
834 if (ps->performance_levels[i].sclk < ps->performance_levels[i - 1].sclk) in ni_apply_state_adjust_rules()
835 ps->performance_levels[i].sclk = ps->performance_levels[i - 1].sclk; in ni_apply_state_adjust_rules()
2056 sclk->sclk_value = engine_clock; in ni_calculate_sclk_params()
2069 NISLANDS_SMC_SCLK_VALUE *sclk) in ni_populate_sclk_value() argument
2098 u32 sclk = 0; in ni_init_smc_spll_table() local
2146 sclk += 512; in ni_init_smc_spll_table()
2322 ret = ni_populate_sclk_value(rdev, pl->sclk, &level->sclk); in ni_convert_power_level_to_smc()
3976 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk = pl->sclk; in ni_parse_pplib_clock_info()
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| H A D | kv_dpm.c | 1970 table->sclk = in kv_construct_max_power_limits_table()
2085 if (sclk < min) in kv_get_sleep_divider_id_from_clock()
2185 if (ps->levels[i].sclk < sclk) in kv_apply_state_adjust_rules()
2186 ps->levels[i].sclk = sclk; in kv_apply_state_adjust_rules()
2613 u32 sclk; in kv_parse_pplib_clock_info() local
2617 pl->sclk = sclk; in kv_parse_pplib_clock_info()
2704 u32 sclk; in kv_parse_power_table() local
2710 rdev->pm.dpm.vce_states[i].sclk = sclk; in kv_parse_power_table()
2803 u32 sclk, tmp; in kv_dpm_debugfs_print_current_performance_level() local
2826 u32 sclk; in kv_dpm_get_current_sclk() local
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| H A D | sumo_dpm.c | 793 pi->acpi_pl.sclk, in sumo_program_acpi_power_level()
1007 u32 sclk, in sumo_get_sleep_divider_id_from_clock() argument
1016 if (sclk < min) in sumo_get_sleep_divider_id_from_clock()
1119 ps->levels[i].sclk = in sumo_apply_state_adjust_rules()
1439 u32 sclk; in sumo_parse_pplib_clock_info() local
1443 pl->sclk = sclk; in sumo_parse_pplib_clock_info()
1808 i, pl->sclk, in sumo_dpm_print_power_state()
1829 current_index, pl->sclk, in sumo_dpm_debugfs_print_current_performance_level()
1837 current_index, pl->sclk, in sumo_dpm_debugfs_print_current_performance_level()
1854 return pl->sclk; in sumo_dpm_get_current_sclk()
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| H A D | si_dpm.c | 2853 u32 sclk = 0; in si_init_smc_spll_table() local
3037 if (ps->performance_levels[i].sclk > max_limits->sclk) in si_apply_state_adjust_rules()
3038 ps->performance_levels[i].sclk = max_limits->sclk; in si_apply_state_adjust_rules()
3091 sclk = ps->performance_levels[0].sclk; in si_apply_state_adjust_rules()
3103 ps->performance_levels[0].sclk = sclk; in si_apply_state_adjust_rules()
3109 sclk = ps->performance_levels[0].sclk; in si_apply_state_adjust_rules()
3111 if (sclk < ps->performance_levels[i].sclk) in si_apply_state_adjust_rules()
3112 sclk = ps->performance_levels[i].sclk; in si_apply_state_adjust_rules()
3115 ps->performance_levels[i].sclk = sclk; in si_apply_state_adjust_rules()
4216 (sclk <= limits->entries[i].sclk) && in si_populate_phase_shedding_value()
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| H A D | rv6xx_dpm.c | 440 state->low.sclk; in rv6xx_calculate_engine_speed_stepping_parameters()
442 state->medium.sclk; in rv6xx_calculate_engine_speed_stepping_parameters()
444 state->high.sclk; in rv6xx_calculate_engine_speed_stepping_parameters()
1029 state->medium.sclk, in rv6xx_calculate_ap()
1037 state->high.sclk, in rv6xx_calculate_ap()
1440 new_state->low.sclk, in rv6xx_generate_low_step()
1523 if (new_state->high.sclk >= current_state->high.sclk) in rv6xx_set_uvd_clock_before_set_eng_clock()
1540 if (new_state->high.sclk < current_state->high.sclk) in rv6xx_set_uvd_clock_after_set_eng_clock()
1822 u32 sclk, mclk; in rv6xx_parse_pplib_clock_info() local
1845 pl->sclk = sclk; in rv6xx_parse_pplib_clock_info()
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| H A D | rs690.c | 267 fixed20_12 sclk; member
279 fixed20_12 sclk, core_bandwidth, max_bandwidth; in rs690_crtc_bandwidth_compute() local
297 sclk.full = dfixed_const(selected_sclk); in rs690_crtc_bandwidth_compute()
298 sclk.full = dfixed_div(sclk, a); in rs690_crtc_bandwidth_compute()
302 core_bandwidth.full = dfixed_div(rdev->pm.sclk, a); in rs690_crtc_bandwidth_compute()
386 sclk.full = dfixed_mul(max_bandwidth, a); in rs690_crtc_bandwidth_compute()
388 sclk.full = dfixed_div(a, sclk); in rs690_crtc_bandwidth_compute()
395 chunk_time.full = dfixed_mul(sclk, a); in rs690_crtc_bandwidth_compute()
483 fill_rate.full = dfixed_div(wm0->sclk, a); in rs690_compute_mode_priority()
531 fill_rate.full = dfixed_div(wm0->sclk, a); in rs690_compute_mode_priority()
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| H A D | ci_dpm.c | 836 u32 sclk, mclk; in ci_apply_state_adjust_rules() local
867 if (ps->performance_levels[i].sclk > max_limits->sclk) in ci_apply_state_adjust_rules()
868 ps->performance_levels[i].sclk = max_limits->sclk; in ci_apply_state_adjust_rules()
876 sclk = ps->performance_levels[0].sclk; in ci_apply_state_adjust_rules()
879 sclk = ps->performance_levels[0].sclk; in ci_apply_state_adjust_rules()
884 sclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].sclk; in ci_apply_state_adjust_rules()
889 ps->performance_levels[0].sclk = sclk; in ci_apply_state_adjust_rules()
2423 if (sclk < limits->entries[i].sclk) { in ci_populate_phase_value_based_on_sclk()
2557 u32 sclk, in ci_populate_memory_timing_parameters() argument
5656 rdev->pm.dpm.vce_states[i].sclk = sclk; in ci_parse_power_table()
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| H A D | rs780_dpm.c | 752 u32 sclk; in rs780_parse_pplib_clock_info() local
754 sclk = le16_to_cpu(clock_info->rs780.usLowEngineClockLow); in rs780_parse_pplib_clock_info()
755 sclk |= clock_info->rs780.ucLowEngineClockHigh << 16; in rs780_parse_pplib_clock_info()
756 ps->sclk_low = sclk; in rs780_parse_pplib_clock_info()
757 sclk = le16_to_cpu(clock_info->rs780.usHighEngineClockLow); in rs780_parse_pplib_clock_info()
758 sclk |= clock_info->rs780.ucHighEngineClockHigh << 16; in rs780_parse_pplib_clock_info()
759 ps->sclk_high = sclk; in rs780_parse_pplib_clock_info()
990 u32 sclk = (rdev->clock.spll.reference_freq * current_fb_div) / in rs780_dpm_debugfs_print_current_performance_level() local
996 if (sclk < (ps->sclk_low + 500)) in rs780_dpm_debugfs_print_current_performance_level()
1012 u32 sclk = (rdev->clock.spll.reference_freq * current_fb_div) / in rs780_dpm_get_current_sclk() local
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| H A D | radeon_atombios.c | 2466 u32 sclk, mclk; in radeon_atombios_parse_pplib_clock_info() local
2472 sclk |= clock_info->sumo.ucEngineClockHigh << 16; in radeon_atombios_parse_pplib_clock_info()
2473 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk; in radeon_atombios_parse_pplib_clock_info()
2477 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk; in radeon_atombios_parse_pplib_clock_info()
2481 sclk |= clock_info->ci.ucEngineClockHigh << 16; in radeon_atombios_parse_pplib_clock_info()
2485 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk; in radeon_atombios_parse_pplib_clock_info()
2490 sclk |= clock_info->si.ucEngineClockHigh << 16; in radeon_atombios_parse_pplib_clock_info()
2494 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk; in radeon_atombios_parse_pplib_clock_info()
2507 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk; in radeon_atombios_parse_pplib_clock_info()
2516 sclk |= clock_info->r600.ucEngineClockHigh << 16; in radeon_atombios_parse_pplib_clock_info()
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| H A D | cypress_dpm.c | 691 ret = rv740_populate_sclk_value(rdev, pl->sclk, &level->sclk); in cypress_convert_power_level_to_smc()
725 pl->sclk, in cypress_convert_power_level_to_smc()
732 pl->sclk, in cypress_convert_power_level_to_smc()
933 new_state->low.sclk, in cypress_program_memory_timing_parameters()
936 new_state->medium.sclk, in cypress_program_memory_timing_parameters()
939 new_state->high.sclk, in cypress_program_memory_timing_parameters()
1275 table->initialState.levels[0].sclk.sclk_value = in cypress_populate_smc_initial_state()
1276 cpu_to_be32(initial_state->low.sclk); in cypress_populate_smc_initial_state()
1447 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL = in cypress_populate_smc_acpi_state()
1449 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 = in cypress_populate_smc_acpi_state()
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| H A D | rv770_dpm.h | 142 u32 sclk; member
181 RV770_SMC_SCLK_VALUE *sclk);
202 RV770_SMC_SCLK_VALUE *sclk);
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| H A D | radeon_clocks.c | 39 uint32_t fb_div, ref_div, post_div, sclk; in radeon_legacy_get_engine_clock() local
52 sclk = fb_div / ref_div; in radeon_legacy_get_engine_clock()
56 sclk >>= 1; in radeon_legacy_get_engine_clock()
58 sclk >>= 2; in radeon_legacy_get_engine_clock()
60 sclk >>= 3; in radeon_legacy_get_engine_clock()
62 return sclk; in radeon_legacy_get_engine_clock()
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| H A D | sumo_dpm.h | 32 u32 sclk; member
207 u32 sclk,
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| H A D | rv515.c | 946 fixed20_12 sclk; member
958 fixed20_12 sclk; in rv515_crtc_bandwidth_compute() local
976 sclk.full = dfixed_const(selected_sclk); in rv515_crtc_bandwidth_compute()
977 sclk.full = dfixed_div(sclk, a); in rv515_crtc_bandwidth_compute()
1044 chunk_time.full = dfixed_div(a, sclk); in rv515_crtc_bandwidth_compute()
1129 fill_rate.full = dfixed_div(wm0->sclk, a); in rv515_compute_mode_priority()
1177 fill_rate.full = dfixed_div(wm0->sclk, a); in rv515_compute_mode_priority()
1204 fill_rate.full = dfixed_div(wm1->sclk, a); in rv515_compute_mode_priority()
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| H A D | radeon_pm.c | 173 u32 sclk, mclk; in radeon_set_power_state() local
182 clock_info[rdev->pm.requested_clock_mode_index].sclk; in radeon_set_power_state()
183 if (sclk > rdev->pm.default_sclk) in radeon_set_power_state()
184 sclk = rdev->pm.default_sclk; in radeon_set_power_state()
205 if (sclk < rdev->pm.current_sclk) in radeon_set_power_state()
222 if (sclk != rdev->pm.current_sclk) { in radeon_set_power_state()
224 radeon_set_engine_clock(rdev, sclk); in radeon_set_power_state()
226 rdev->pm.current_sclk = sclk; in radeon_set_power_state()
227 DRM_DEBUG_DRIVER("Setting: e: %d\n", sclk); in radeon_set_power_state()
343 clock_info->sclk * 10); in radeon_pm_print_states()
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| /dragonfly/sys/dev/drm/amd/amdgpu/ |
| H A D | si_dpm.c | 3497 ps->performance_levels[i].sclk = max_limits->sclk; in si_apply_state_adjust_rules()
3550 sclk = ps->performance_levels[0].sclk; in si_apply_state_adjust_rules()
3562 ps->performance_levels[0].sclk = sclk; in si_apply_state_adjust_rules()
3568 sclk = ps->performance_levels[0].sclk; in si_apply_state_adjust_rules()
3570 if (sclk < ps->performance_levels[i].sclk) in si_apply_state_adjust_rules()
3571 sclk = ps->performance_levels[i].sclk; in si_apply_state_adjust_rules()
3574 ps->performance_levels[i].sclk = sclk; in si_apply_state_adjust_rules()
4679 (sclk <= limits->entries[i].sclk) && in si_populate_phase_shedding_value()
7295 adev->pm.dpm.vce_states[i].sclk = sclk; in si_parse_power_table()
7930 (si_cpl1->sclk == si_cpl2->sclk) && in si_are_power_levels_equal()
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| /dragonfly/sys/dev/drm/amd/powerplay/hwmgr/ |
| H A D | ppatomctrl.h | 291 …oltage_evv_on_sclk(struct pp_hwmgr *hwmgr, uint8_t voltage_type, uint32_t sclk, uint16_t virtual_v…
314 uint32_t sclk, uint16_t virtual_voltage_Id, uint16_t *voltage, uint16_t dpm_level, bool debug);
319 uint32_t sclk, uint16_t virtual_voltage_Id, uint32_t *voltage);
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| H A D | smu_helper.c | 414 uint16_t virtual_voltage_id, int32_t *sclk) in phm_get_sclk_for_voltage_evv() argument
435 *sclk = table_info->vdd_dep_on_sclk->entries[entry_id].clk; in phm_get_sclk_for_voltage_evv()
522 uint32_t sclk, uint16_t id, uint16_t *voltage) in phm_get_voltage_evv_on_sclk() argument
530 ret = atomctrl_get_voltage_evv_on_sclk(hwmgr, voltage_type, sclk, id, voltage); in phm_get_voltage_evv_on_sclk()
534 ret = atomctrl_get_voltage_evv_on_sclk_ai(hwmgr, voltage_type, sclk, id, &vol); in phm_get_voltage_evv_on_sclk()
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| H A D | smu7_hwmgr.c | 1704 uint32_t sclk = 0; in smu7_get_evv_voltages() local
1724 sclk += 5000; in smu7_get_evv_voltages()
1758 sclk += 5000; in smu7_get_evv_voltages()
1766 sclk, vv_id, &vddc) == 0) { in smu7_get_evv_voltages()
2107 hwmgr->dyn_state.max_clock_voltage_on_ac.sclk = table_info->max_clock_voltage_on_ac.sclk; in smu7_set_private_data_based_on_pptable_v1()
2891 uint32_t sclk; in smu7_apply_state_adjust_rules() local
2972 sclk = (minimum_clocks.engineClock > max_limits->sclk) ? in smu7_apply_state_adjust_rules()
3540 *((uint32_t *)value) = sclk; in smu7_read_sensor()
3642 uint32_t sclk, max_sclk = 0; in smu7_get_maximum_link_speed() local
3648 if (max_sclk < sclk) in smu7_get_maximum_link_speed()
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| /dragonfly/sys/dev/drm/amd/display/dc/calcs/ |
| H A D | dce_calcs.c | 99 struct bw_fixed sclk[8]; in calculate_bandwidth() local
126 sclk[s_low] = vbios->low_sclk; in calculate_bandwidth()
127 sclk[s_mid1] = vbios->mid1_sclk; in calculate_bandwidth()
128 sclk[s_mid2] = vbios->mid2_sclk; in calculate_bandwidth()
129 sclk[s_mid3] = vbios->mid3_sclk; in calculate_bandwidth()
130 sclk[s_mid4] = vbios->mid4_sclk; in calculate_bandwidth()
131 sclk[s_mid5] = vbios->mid5_sclk; in calculate_bandwidth()
132 sclk[s_mid6] = vbios->mid6_sclk; in calculate_bandwidth()
133 sclk[s_high] = vbios->high_sclk; in calculate_bandwidth()
1622 && bw_ltn(data->required_sclk, sclk[s_high])) { in calculate_bandwidth()
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