/dragonfly/sys/dev/drm/amd/powerplay/hwmgr/ |
H A D | smu7_hwmgr.c | 631 &data->dpm_table.sclk_table, in smu7_reset_dpm_tables() 694 data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count].value = in smu7_setup_dpm_tables_v0() 788 data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count].value = in smu7_setup_dpm_tables_v1() 791 data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count].enabled = in smu7_setup_dpm_tables_v1() 3597 struct smu7_single_dpm_table *sclk_table = &(data->dpm_table.sclk_table); in smu7_find_dpm_states_clocks_in_dpm_table() local 3611 if (i >= sclk_table->count) in smu7_find_dpm_states_clocks_in_dpm_table() 4431 struct smu7_single_dpm_table *sclk_table = &(data->dpm_table.sclk_table); in smu7_print_clock_levels() local 4555 struct smu7_single_dpm_table *sclk_table = &(data->dpm_table.sclk_table); in smu7_get_sclk_od() local 4560 value = (sclk_table->dpm_levels[sclk_table->count - 1].value - in smu7_get_sclk_od() 4763 struct smu7_single_dpm_table *sclk_table = &(data->dpm_table.sclk_table); in smu7_get_max_high_clocks() local [all …]
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H A D | process_pptables_v1_0.c | 417 phm_ppt_v1_clock_voltage_dependency_table *sclk_table; in get_sclk_voltage_dependency_table() local 431 sclk_table = kzalloc(table_size, GFP_KERNEL); in get_sclk_voltage_dependency_table() 433 if (NULL == sclk_table) in get_sclk_voltage_dependency_table() 436 sclk_table->count = (uint32_t)tonga_table->ucNumEntries; in get_sclk_voltage_dependency_table() 444 entries, sclk_table, i); in get_sclk_voltage_dependency_table() 463 sclk_table = kzalloc(table_size, GFP_KERNEL); in get_sclk_voltage_dependency_table() 465 if (NULL == sclk_table) in get_sclk_voltage_dependency_table() 468 sclk_table->count = (uint32_t)polaris_table->ucNumEntries; in get_sclk_voltage_dependency_table() 476 entries, sclk_table, i); in get_sclk_voltage_dependency_table() 486 *pp_tonga_sclk_dep_table = sclk_table; in get_sclk_voltage_dependency_table()
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H A D | smu7_hwmgr.h | 104 struct smu7_single_dpm_table sclk_table; member
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H A D | smu8_hwmgr.c | 1512 struct phm_clock_voltage_dependency_table *sclk_table = in smu8_print_clock_levels() local 1524 for (i = 0; i < sclk_table->count; i++) in smu8_print_clock_levels() 1526 i, sclk_table->entries[i].clk / 100, in smu8_print_clock_levels()
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H A D | vega10_hwmgr.c | 4246 struct vega10_single_dpm_table *sclk_table = &(data->dpm_table.gfx_table); in vega10_print_clock_levels() local 4261 for (i = 0; i < sclk_table->count; i++) in vega10_print_clock_levels() 4263 i, sclk_table->dpm_levels[i].value / 100, in vega10_print_clock_levels() 4499 struct vega10_single_dpm_table *sclk_table = &(data->dpm_table.gfx_table); in vega10_get_sclk_od() local 4504 value = (sclk_table->dpm_levels[sclk_table->count - 1].value - in vega10_get_sclk_od()
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H A D | vega12_hwmgr.c | 2242 struct vega12_single_dpm_table *sclk_table = &(data->dpm_table.gfx_table); 2247 value = (sclk_table->dpm_levels[sclk_table->count - 1].value -
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/dragonfly/sys/dev/drm/amd/powerplay/smumgr/ |
H A D | vegam_smumgr.c | 888 for (i = 0; i < dpm_table->sclk_table.count; i++) { in vegam_populate_all_graphic_levels() 891 dpm_table->sclk_table.dpm_levels[i].value, in vegam_populate_all_graphic_levels() 909 (uint8_t)dpm_table->sclk_table.count; in vegam_populate_all_graphic_levels() 913 for (i = 0; i < dpm_table->sclk_table.count; i++) in vegam_populate_all_graphic_levels() 922 for (i = 0; i < dpm_table->sclk_table.count; i++) in vegam_populate_all_graphic_levels() 947 for (i = 2; i < dpm_table->sclk_table.count; i++) in vegam_populate_all_graphic_levels() 1301 hw_data->dpm_table.sclk_table.dpm_levels[i].value, in vegam_program_memory_timing_parameters() 1516 for (i = 0; i < sclk_table->count; i++) { in vegam_populate_clock_stretcher_data_table() 1518 sclk_table->entries[i].cks_enable << i; in vegam_populate_clock_stretcher_data_table() 1637 for (i = 0; i < sclk_table->count; i++) { in vegam_populate_avfs_parameters() [all …]
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H A D | polaris10_smumgr.c | 1000 for (i = 0; i < dpm_table->sclk_table.count; i++) { in polaris10_populate_all_graphic_levels() 1003 dpm_table->sclk_table.dpm_levels[i].value, in polaris10_populate_all_graphic_levels() 1018 (uint8_t)dpm_table->sclk_table.count; in polaris10_populate_all_graphic_levels() 1028 for (i = 0; i < dpm_table->sclk_table.count; i++) in polaris10_populate_all_graphic_levels() 1053 for (i = 2; i < dpm_table->sclk_table.count; i++) in polaris10_populate_all_graphic_levels() 1368 for (i = 0; i < hw_data->dpm_table.sclk_table.count; i++) { in polaris10_program_memory_timing_parameters() 1371 hw_data->dpm_table.sclk_table.dpm_levels[i].value, in polaris10_program_memory_timing_parameters() 1457 result = phm_find_boot_level(&(data->dpm_table.sclk_table), in polaris10_populate_smc_boot_level() 1554 for (i = 0; i < sclk_table->count; i++) { in polaris10_populate_clock_stretcher_data_table() 1556 sclk_table->entries[i].cks_enable << i; in polaris10_populate_clock_stretcher_data_table() [all …]
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H A D | tonga_smumgr.c | 700 for (i = 0; i < dpm_table->sclk_table.count; i++) { in tonga_populate_all_graphic_levels() 702 dpm_table->sclk_table.dpm_levels[i].value, in tonga_populate_all_graphic_levels() 716 if (dpm_table->sclk_table.count > 1) in tonga_populate_all_graphic_levels() 721 (uint8_t)dpm_table->sclk_table.count; in tonga_populate_all_graphic_levels() 730 for (i = 0; i < dpm_table->sclk_table.count; i++) { in tonga_populate_all_graphic_levels() 760 for (i = 2; i < dpm_table->sclk_table.count; i++) in tonga_populate_all_graphic_levels() 1487 for (i = 0; i < data->dpm_table.sclk_table.count; i++) { in tonga_program_memory_timing_parameters() 1610 for (i = 0; i < sclk_table->count; i++) { in tonga_populate_clock_stretcher_data_table() 1612 sclk_table->entries[i].cks_enable << i; in tonga_populate_clock_stretcher_data_table() 1615 (sclk_table->entries[i].clk/100) / 10000) * 1000 / in tonga_populate_clock_stretcher_data_table() [all …]
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H A D | fiji_smumgr.c | 1036 for (i = 0; i < dpm_table->sclk_table.count; i++) { in fiji_populate_all_graphic_levels() 1038 dpm_table->sclk_table.dpm_levels[i].value, in fiji_populate_all_graphic_levels() 1052 levels[dpm_table->sclk_table.count - 1].DisplayWatermark = in fiji_populate_all_graphic_levels() 1056 (uint8_t)dpm_table->sclk_table.count; in fiji_populate_all_graphic_levels() 1065 for (i = 0; i < dpm_table->sclk_table.count; i++) in fiji_populate_all_graphic_levels() 1090 for (i = 2; i < dpm_table->sclk_table.count; i++) in fiji_populate_all_graphic_levels() 1329 data->dpm_table.sclk_table.dpm_levels[0].value; in fiji_populate_smc_acpi_level() 1546 for (i = 0; i < data->dpm_table.sclk_table.count; i++) { in fiji_program_memory_timing_parameters() 1549 data->dpm_table.sclk_table.dpm_levels[i].value, in fiji_program_memory_timing_parameters() 1715 for (i = 0; i < sclk_table->count; i++) { in fiji_populate_clock_stretcher_data_table() [all …]
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H A D | iceland_smumgr.c | 980 for (i = 0; i < dpm_table->sclk_table.count; i++) { in iceland_populate_all_graphic_levels() 982 dpm_table->sclk_table.dpm_levels[i].value, in iceland_populate_all_graphic_levels() 996 if (dpm_table->sclk_table.count > 1) in iceland_populate_all_graphic_levels() 997 smu_data->smc_state_table.GraphicsLevel[dpm_table->sclk_table.count-1].DisplayWatermark = in iceland_populate_all_graphic_levels() 1001 (uint8_t)dpm_table->sclk_table.count; in iceland_populate_all_graphic_levels() 1003 phm_get_dpm_level_enable_mask_value(&dpm_table->sclk_table); in iceland_populate_all_graphic_levels() 1026 for (i = 2; i < dpm_table->sclk_table.count; i++) { in iceland_populate_all_graphic_levels() 1620 for (i = 0; i < data->dpm_table.sclk_table.count; i++) { in iceland_program_memory_timing_parameters() 1623 (hwmgr, data->dpm_table.sclk_table.dpm_levels[i].value, in iceland_program_memory_timing_parameters() 1656 result = phm_find_boot_level(&(data->dpm_table.sclk_table), in iceland_populate_smc_boot_level()
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H A D | ci_smumgr.c | 484 for (i = 0; i < dpm_table->sclk_table.count; i++) { in ci_populate_all_graphic_levels() 486 dpm_table->sclk_table.dpm_levels[i].value, in ci_populate_all_graphic_levels() 492 if (i == (dpm_table->sclk_table.count - 1)) in ci_populate_all_graphic_levels() 499 smu_data->smc_state_table.GraphicsDpmLevelCount = (u8)dpm_table->sclk_table.count; in ci_populate_all_graphic_levels() 501 phm_get_dpm_level_enable_mask_value(&dpm_table->sclk_table); in ci_populate_all_graphic_levels() 1657 for (i = 0; i < data->dpm_table.sclk_table.count; i++) { in ci_program_memory_timing_parameters() 1660 (hwmgr, data->dpm_table.sclk_table.dpm_levels[i].value, in ci_program_memory_timing_parameters() 1693 result = phm_find_boot_level(&(data->dpm_table.sclk_table), in ci_populate_smc_boot_level()
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/dragonfly/sys/dev/drm/radeon/ |
H A D | ci_dpm.c | 3498 &pi->dpm_table.sclk_table, in ci_setup_default_dpm_tables() 3513 pi->dpm_table.sclk_table.count = 0; in ci_setup_default_dpm_tables() 3516 (pi->dpm_table.sclk_table.dpm_levels[pi->dpm_table.sclk_table.count-1].value != in ci_setup_default_dpm_tables() 3518 pi->dpm_table.sclk_table.dpm_levels[pi->dpm_table.sclk_table.count].value = in ci_setup_default_dpm_tables() 3520 pi->dpm_table.sclk_table.dpm_levels[pi->dpm_table.sclk_table.count].enabled = in ci_setup_default_dpm_tables() 3522 pi->dpm_table.sclk_table.count++; in ci_setup_default_dpm_tables() 3799 &pi->dpm_table.sclk_table, in ci_trim_dpm_states() 3894 struct ci_single_dpm_table *sclk_table = &pi->dpm_table.sclk_table; in ci_find_dpm_states_clocks_in_dpm_table() local 3902 for (i = 0; i < sclk_table->count; i++) { in ci_find_dpm_states_clocks_in_dpm_table() 3907 if (i >= sclk_table->count) { in ci_find_dpm_states_clocks_in_dpm_table() [all …]
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H A D | ci_dpm.h | 68 struct ci_single_dpm_table sclk_table; member
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