/dragonfly/sys/dev/drm/radeon/ |
H A D | radeon_object.c | 592 lobj->tiling_flags = bo->tiling_flags; in radeon_bo_list_validate() 597 lobj->tiling_flags = lobj->robj->tiling_flags; in radeon_bo_list_validate() 613 if (!bo->tiling_flags) in radeon_bo_get_surface_reg() 652 radeon_set_surface_reg(rdev, i, bo->tiling_flags, bo->pitch, in radeon_bo_get_surface_reg() 674 uint32_t tiling_flags, uint32_t pitch) in radeon_bo_set_tiling_flags() argument 682 bankw = (tiling_flags >> RADEON_TILING_EG_BANKW_SHIFT) & RADEON_TILING_EG_BANKW_MASK; in radeon_bo_set_tiling_flags() 727 bo->tiling_flags = tiling_flags; in radeon_bo_set_tiling_flags() 734 uint32_t *tiling_flags, in radeon_bo_get_tiling_flags() argument 739 if (tiling_flags) in radeon_bo_get_tiling_flags() 740 *tiling_flags = bo->tiling_flags; in radeon_bo_get_tiling_flags() [all …]
|
H A D | radeon_fb.c | 140 u32 tiling_flags = 0; in radeonfb_create_pinned_object() local 166 tiling_flags = RADEON_TILING_MACRO; in radeonfb_create_pinned_object() 171 tiling_flags |= RADEON_TILING_SWAP_32BIT; in radeonfb_create_pinned_object() 174 tiling_flags |= RADEON_TILING_SWAP_16BIT; in radeonfb_create_pinned_object() 180 if (tiling_flags) { in radeonfb_create_pinned_object() 182 tiling_flags | RADEON_TILING_SURFACE, in radeonfb_create_pinned_object()
|
H A D | r200.c | 221 if (reloc->tiling_flags & RADEON_TILING_MACRO) in r200_packet0_check() 223 if (reloc->tiling_flags & RADEON_TILING_MICRO) in r200_packet0_check() 293 if (reloc->tiling_flags & RADEON_TILING_MACRO) in r200_packet0_check() 295 if (reloc->tiling_flags & RADEON_TILING_MICRO) in r200_packet0_check()
|
H A D | radeon_object.h | 147 u32 tiling_flags, u32 pitch); 149 u32 *tiling_flags, u32 *pitch);
|
H A D | r300.c | 713 if (reloc->tiling_flags & RADEON_TILING_MACRO) in r300_packet0_check() 715 if (reloc->tiling_flags & RADEON_TILING_MICRO) in r300_packet0_check() 717 else if (reloc->tiling_flags & RADEON_TILING_MICRO_SQUARE) in r300_packet0_check() 782 if (reloc->tiling_flags & RADEON_TILING_MACRO) in r300_packet0_check() 784 if (reloc->tiling_flags & RADEON_TILING_MICRO) in r300_packet0_check() 786 else if (reloc->tiling_flags & RADEON_TILING_MICRO_SQUARE) in r300_packet0_check() 867 if (reloc->tiling_flags & RADEON_TILING_MACRO) in r300_packet0_check() 869 if (reloc->tiling_flags & RADEON_TILING_MICRO) in r300_packet0_check() 871 else if (reloc->tiling_flags & RADEON_TILING_MICRO_SQUARE) in r300_packet0_check()
|
H A D | radeon_legacy_crtc.c | 384 uint32_t tiling_flags; in radeon_crtc_do_set_base() local 466 radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL); in radeon_crtc_do_set_base() 468 if (tiling_flags & RADEON_TILING_MICRO) in radeon_crtc_do_set_base() 485 if (tiling_flags & RADEON_TILING_MACRO) { in radeon_crtc_do_set_base() 501 if (tiling_flags & RADEON_TILING_MACRO) { in radeon_crtc_do_set_base()
|
H A D | evergreen_cs.c | 91 static u32 evergreen_cs_get_aray_mode(u32 tiling_flags) in evergreen_cs_get_aray_mode() argument 93 if (tiling_flags & RADEON_TILING_MACRO) in evergreen_cs_get_aray_mode() 95 else if (tiling_flags & RADEON_TILING_MICRO) in evergreen_cs_get_aray_mode() 1180 if (reloc->tiling_flags & RADEON_TILING_MACRO) { in evergreen_cs_handle_reg() 1183 evergreen_tiling_fields(reloc->tiling_flags, in evergreen_cs_handle_reg() 1444 if (reloc->tiling_flags & RADEON_TILING_MACRO) { in evergreen_cs_handle_reg() 1447 evergreen_tiling_fields(reloc->tiling_flags, in evergreen_cs_handle_reg() 1472 if (reloc->tiling_flags & RADEON_TILING_MACRO) { in evergreen_cs_handle_reg() 1475 evergreen_tiling_fields(reloc->tiling_flags, in evergreen_cs_handle_reg() 2361 if (reloc->tiling_flags & RADEON_TILING_MACRO) { in evergreen_packet3_check() [all …]
|
H A D | atombios_crtc.c | 1153 uint32_t fb_format, fb_pitch_pixels, tiling_flags; in dce4_crtc_do_set_base() local 1195 radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL); in dce4_crtc_do_set_base() 1268 if (tiling_flags & RADEON_TILING_MACRO) { in dce4_crtc_do_set_base() 1269 evergreen_tiling_fields(tiling_flags, &bankw, &bankh, &mtaspect, &tile_split); in dce4_crtc_do_set_base() 1342 } else if (tiling_flags & RADEON_TILING_MICRO) in dce4_crtc_do_set_base() 1471 uint32_t fb_format, fb_pitch_pixels, tiling_flags; in avivo_crtc_do_set_base() local 1511 radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL); in avivo_crtc_do_set_base() 1572 if (tiling_flags & RADEON_TILING_MACRO) in avivo_crtc_do_set_base() 1574 else if (tiling_flags & RADEON_TILING_MICRO) in avivo_crtc_do_set_base() 1577 if (tiling_flags & RADEON_TILING_MACRO) in avivo_crtc_do_set_base() [all …]
|
H A D | r100.c | 1293 if (reloc->tiling_flags & RADEON_TILING_MACRO) in r100_reloc_pitch_offset() 1635 if (reloc->tiling_flags & RADEON_TILING_MACRO) in r100_packet0_check() 1637 if (reloc->tiling_flags & RADEON_TILING_MICRO) in r100_packet0_check() 3104 uint32_t tiling_flags, uint32_t pitch, in r100_set_surface_reg() argument 3114 if (tiling_flags & RADEON_TILING_MACRO) in r100_set_surface_reg() 3121 if (tiling_flags & (RADEON_TILING_MACRO)) in r100_set_surface_reg() 3123 if (tiling_flags & RADEON_TILING_MICRO) in r100_set_surface_reg() 3126 if (tiling_flags & RADEON_TILING_MACRO) in r100_set_surface_reg() 3128 if (tiling_flags & RADEON_TILING_MICRO) in r100_set_surface_reg() 3132 if (tiling_flags & RADEON_TILING_SWAP_16BIT) in r100_set_surface_reg() [all …]
|
H A D | r600_cs.c | 1044 if (reloc->tiling_flags & RADEON_TILING_MACRO) { in r600_cs_check_reg() 1143 if (reloc->tiling_flags & RADEON_TILING_MACRO) { in r600_cs_check_reg() 1146 } else if (reloc->tiling_flags & RADEON_TILING_MICRO) { in r600_cs_check_reg() 1474 u32 tiling_flags) in r600_check_texture_resource() argument 1496 if (tiling_flags & RADEON_TILING_MACRO) in r600_check_texture_resource() 1498 else if (tiling_flags & RADEON_TILING_MICRO) in r600_check_texture_resource() 1967 if (reloc->tiling_flags & RADEON_TILING_MACRO) in r600_packet3_check() 1969 else if (reloc->tiling_flags & RADEON_TILING_MICRO) in r600_packet3_check() 1985 reloc->tiling_flags); in r600_packet3_check()
|
H A D | radeon_gem.c | 517 r = radeon_bo_set_tiling_flags(robj, args->tiling_flags, args->pitch); in radeon_gem_set_tiling_ioctl() 538 radeon_bo_get_tiling_flags(rbo, &args->tiling_flags, &args->pitch); in radeon_gem_get_tiling_ioctl()
|
H A D | radeon_vm.c | 146 list[0].tiling_flags = 0; in radeon_vm_get_bos() 158 list[idx].tiling_flags = 0; in radeon_vm_get_bos()
|
H A D | radeon_display.c | 485 uint32_t tiling_flags, pitch_pixels; in radeon_crtc_page_flip_target() local 533 radeon_bo_get_tiling_flags(new_rbo, &tiling_flags, NULL); in radeon_crtc_page_flip_target() 541 if (tiling_flags & RADEON_TILING_MACRO) { in radeon_crtc_page_flip_target()
|
H A D | radeon.h | 357 extern void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw, 474 uint32_t tiling_flags; member 506 u32 tiling_flags; member 1946 uint32_t tiling_flags, uint32_t pitch,
|
H A D | radeon_asic.h | 91 uint32_t tiling_flags, uint32_t pitch, 341 uint32_t tiling_flags, uint32_t pitch,
|
H A D | evergreen.c | 1096 void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw, in evergreen_tiling_fields() argument 1100 *bankw = (tiling_flags >> RADEON_TILING_EG_BANKW_SHIFT) & RADEON_TILING_EG_BANKW_MASK; in evergreen_tiling_fields() 1101 *bankh = (tiling_flags >> RADEON_TILING_EG_BANKH_SHIFT) & RADEON_TILING_EG_BANKH_MASK; in evergreen_tiling_fields() 1102 …*mtaspect = (tiling_flags >> RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT) & RADEON_TILING_EG_MACRO_TI… in evergreen_tiling_fields() 1103 …*tile_split = (tiling_flags >> RADEON_TILING_EG_TILE_SPLIT_SHIFT) & RADEON_TILING_EG_TILE_SPLIT_MA… in evergreen_tiling_fields()
|
H A D | r600.c | 3038 uint32_t tiling_flags, uint32_t pitch, in r600_set_surface_reg() argument
|
/dragonfly/sys/dev/drm/amd/amdgpu/ |
H A D | amdgpu_fb.c | 136 u32 tiling_flags = 0, domain; in amdgpufb_create_pinned_object() local 164 tiling_flags = AMDGPU_TILING_SET(ARRAY_MODE, GRPH_ARRAY_2D_TILED_THIN1); in amdgpufb_create_pinned_object() 170 if (tiling_flags) { in amdgpufb_create_pinned_object() 172 tiling_flags); in amdgpufb_create_pinned_object()
|
H A D | amdgpu_object.h | 87 u64 tiling_flags; member 269 int amdgpu_bo_set_tiling_flags(struct amdgpu_bo *bo, u64 tiling_flags); 270 void amdgpu_bo_get_tiling_flags(struct amdgpu_bo *bo, u64 *tiling_flags);
|
H A D | amdgpu_object.c | 1130 int amdgpu_bo_set_tiling_flags(struct amdgpu_bo *bo, u64 tiling_flags) in amdgpu_bo_set_tiling_flags() argument 1135 AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT) > 6) in amdgpu_bo_set_tiling_flags() 1138 bo->tiling_flags = tiling_flags; in amdgpu_bo_set_tiling_flags() 1150 void amdgpu_bo_get_tiling_flags(struct amdgpu_bo *bo, u64 *tiling_flags) in amdgpu_bo_get_tiling_flags() argument 1154 if (tiling_flags) in amdgpu_bo_get_tiling_flags() 1155 *tiling_flags = bo->tiling_flags; in amdgpu_bo_get_tiling_flags()
|
H A D | dce_v10_0.c | 1831 uint64_t fb_location, tiling_flags; in dce_v10_0_crtc_do_set_base() local 1869 amdgpu_bo_get_tiling_flags(abo, (u64 *)&tiling_flags); in dce_v10_0_crtc_do_set_base() 1872 pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG); in dce_v10_0_crtc_do_set_base() 1951 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_2D_TILED_THIN1) { in dce_v10_0_crtc_do_set_base() 1954 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH); in dce_v10_0_crtc_do_set_base() 1955 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT); in dce_v10_0_crtc_do_set_base() 1956 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT); in dce_v10_0_crtc_do_set_base() 1957 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT); in dce_v10_0_crtc_do_set_base() 1958 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS); in dce_v10_0_crtc_do_set_base() 1971 } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_1D_TILED_THIN1) { in dce_v10_0_crtc_do_set_base()
|
H A D | dce_v11_0.c | 1873 uint64_t fb_location, tiling_flags; in dce_v11_0_crtc_do_set_base() local 1911 amdgpu_bo_get_tiling_flags(abo, (u64 *)&tiling_flags); in dce_v11_0_crtc_do_set_base() 1914 pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG); in dce_v11_0_crtc_do_set_base() 1993 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_2D_TILED_THIN1) { in dce_v11_0_crtc_do_set_base() 1996 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH); in dce_v11_0_crtc_do_set_base() 1997 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT); in dce_v11_0_crtc_do_set_base() 1998 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT); in dce_v11_0_crtc_do_set_base() 1999 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT); in dce_v11_0_crtc_do_set_base() 2000 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS); in dce_v11_0_crtc_do_set_base() 2013 } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_1D_TILED_THIN1) { in dce_v11_0_crtc_do_set_base()
|
H A D | amdgpu_display.c | 159 u64 tiling_flags; in amdgpu_display_crtc_page_flip_target() local 211 amdgpu_bo_get_tiling_flags(new_abo, &tiling_flags); in amdgpu_display_crtc_page_flip_target()
|
/dragonfly/sys/dev/drm/amd/display/amdgpu_dm/ |
H A D | amdgpu_dm.c | 1980 uint64_t *tiling_flags) in get_fb_info() argument 1992 if (tiling_flags) in get_fb_info() 1993 amdgpu_bo_get_tiling_flags(rbo, (u64 *)tiling_flags); in get_fb_info() 2004 uint64_t tiling_flags; in fill_plane_attributes_from_fb() local 2012 &tiling_flags); in fill_plane_attributes_from_fb() 2085 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH); in fill_plane_attributes_from_fb() 2086 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT); in fill_plane_attributes_from_fb() 2089 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS); in fill_plane_attributes_from_fb() 2101 } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) in fill_plane_attributes_from_fb() 2107 AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG); in fill_plane_attributes_from_fb() [all …]
|
/dragonfly/sys/dev/drm/include/uapi/drm/ |
H A D | radeon_drm.h | 858 __u32 tiling_flags; member 864 __u32 tiling_flags; member
|