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Searched refs:uvd_clocks (Results 1 – 8 of 8) sorted by relevance

/dragonfly/sys/dev/drm/amd/powerplay/inc/
H A Dpower_state.h155 struct PP_UVD_CLOCKS uvd_clocks; member
/dragonfly/sys/dev/drm/amd/powerplay/hwmgr/
H A Dsmu10_hwmgr.c759 smu10_ps->uvd_clocks.vclk = ps->uvd_clocks.VCLK; in smu10_dpm_get_pp_table_entry()
760 smu10_ps->uvd_clocks.dclk = ps->uvd_clocks.DCLK; in smu10_dpm_get_pp_table_entry()
H A Dsmu10_hwmgr.h130 struct smu10_uvd_clocks uvd_clocks; member
H A Dsmu8_hwmgr.h146 struct smu8_uvd_clocks uvd_clocks; member
H A Dprocesspptables.c760 ps->uvd_clocks.VCLK = pnon_clock_info->ulVCLK; in init_non_clock_fields()
761 ps->uvd_clocks.DCLK = pnon_clock_info->ulDCLK; in init_non_clock_fields()
763 ps->uvd_clocks.VCLK = 0; in init_non_clock_fields()
764 ps->uvd_clocks.DCLK = 0; in init_non_clock_fields()
H A Dsmu8_hwmgr.c1382 smu8_ps->uvd_clocks.vclk = ps->uvd_clocks.VCLK; in smu8_dpm_get_pp_table_entry()
1383 smu8_ps->uvd_clocks.dclk = ps->uvd_clocks.DCLK; in smu8_dpm_get_pp_table_entry()
H A Dsmu7_hwmgr.c3163 power_state->uvd_clocks.VCLK = 0; in smu7_get_pp_table_entry_callback_func_v1()
3164 power_state->uvd_clocks.DCLK = 0; in smu7_get_pp_table_entry_callback_func_v1()
3256 ps->uvd_clks.vclk = state->uvd_clocks.VCLK; in smu7_get_pp_table_entry_v1()
3257 ps->uvd_clks.dclk = state->uvd_clocks.DCLK; in smu7_get_pp_table_entry_v1()
3404 ps->uvd_clks.vclk = state->uvd_clocks.VCLK; in smu7_get_pp_table_entry_v0()
3405 ps->uvd_clks.dclk = state->uvd_clocks.DCLK; in smu7_get_pp_table_entry_v0()
H A Dvega10_hwmgr.c3020 power_state->uvd_clocks.VCLK = 0; in vega10_get_pp_table_entry_callback_func()
3021 power_state->uvd_clocks.DCLK = 0; in vega10_get_pp_table_entry_callback_func()
3087 ps->uvd_clks.vclk = state->uvd_clocks.VCLK; in vega10_get_pp_table_entry()
3088 ps->uvd_clks.dclk = state->uvd_clocks.DCLK; in vega10_get_pp_table_entry()