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Searched refs:vddc (Results 1 – 25 of 49) sorted by relevance

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/dragonfly/sys/dev/drm/radeon/
H A Dbtc_dpm.c2118 ps->high.vddc = max_limits->vddc; in btc_apply_state_adjust_rules()
2127 ps->medium.vddc = max_limits->vddc; in btc_apply_state_adjust_rules()
2135 if (ps->low.vddc > max_limits->vddc) in btc_apply_state_adjust_rules()
2136 ps->low.vddc = max_limits->vddc; in btc_apply_state_adjust_rules()
2146 vddc = ps->low.vddc; in btc_apply_state_adjust_rules()
2151 vddc = ps->low.vddc; in btc_apply_state_adjust_rules()
2158 ps->low.vddc = vddc; in btc_apply_state_adjust_rules()
2167 if (ps->medium.vddc < ps->low.vddc) in btc_apply_state_adjust_rules()
2168 ps->medium.vddc = ps->low.vddc; in btc_apply_state_adjust_rules()
2171 if (ps->high.vddc < ps->medium.vddc) in btc_apply_state_adjust_rules()
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H A Drv6xx_dpm.c486 pi->hw.vddc[R600_POWER_LEVEL_CTXSW] = state->high.vddc; in rv6xx_calculate_voltage_stepping_parameters()
487 pi->hw.vddc[R600_POWER_LEVEL_HIGH] = state->high.vddc; in rv6xx_calculate_voltage_stepping_parameters()
489 pi->hw.vddc[R600_POWER_LEVEL_LOW] = state->low.vddc; in rv6xx_calculate_voltage_stepping_parameters()
509 if ((state->high.vddc == state->medium.vddc) && in rv6xx_calculate_voltage_stepping_parameters()
517 if ((state->medium.vddc == state->low.vddc) && in rv6xx_calculate_voltage_stepping_parameters()
1208 new_state->low.vddc : old_state->low.vddc; in rv6xx_set_sw_voltage_to_safe()
1312 if (new_state->low.vddc > old_state->low.vddc) in rv6xx_step_voltage_if_increasing()
1327 if (new_state->low.vddc < old_state->low.vddc) in rv6xx_step_voltage_if_decreasing()
1823 u16 vddc; in rv6xx_parse_pplib_clock_info() local
1852 pl->vddc = vddc; in rv6xx_parse_pplib_clock_info()
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H A Dsi_dpm.c2350 state->performance_levels[i-1].vddc, &vddc); in si_populate_power_containment_values()
2359 state->performance_levels[i].vddc, &vddc); in si_populate_power_containment_values()
3039 if (ps->performance_levels[i].vddc > max_limits->vddc) in si_apply_state_adjust_rules()
3040 ps->performance_levels[i].vddc = max_limits->vddc; in si_apply_state_adjust_rules()
3092 vddc = ps->performance_levels[0].vddc; in si_apply_state_adjust_rules()
3105 ps->performance_levels[0].vddc = vddc; in si_apply_state_adjust_rules()
3116 ps->performance_levels[i].vddc = vddc; in si_apply_state_adjust_rules()
3155 max_limits->vddc, &ps->performance_levels[i].vddc); in si_apply_state_adjust_rules()
3161 max_limits->vddc, &ps->performance_levels[i].vddc); in si_apply_state_adjust_rules()
5045 pl->vddc, &level->vddc); in si_convert_power_level_to_smc()
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H A Drv770_dpm.c583 if (vddc <= pi->vddc_table[i].vddc) { in rv770_populate_vddc_value()
669 &level->vddc); in rv770_convert_power_level_to_smc()
1076 initial_state->low.vddc, in rv770_populate_smc_initial_state()
1697 u16 vddc; in rv770_get_max_vddc() local
1702 pi->max_vddc = vddc; in rv770_get_max_vddc()
2224 if (pl->vddc == 0xff01) { in rv7xx_parse_pplib_clock_info()
2226 pl->vddc = pi->max_vddc; in rv7xx_parse_pplib_clock_info()
2230 pi->acpi_vddc = pl->vddc; in rv7xx_parse_pplib_clock_info()
2254 u16 vddc, vddci, mvdd; in rv7xx_parse_pplib_clock_info() local
2258 pl->vddc = vddc; in rv7xx_parse_pplib_clock_info()
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H A Dni_dpm.c812 if (ps->performance_levels[i].vddc > max_limits->vddc) in ni_apply_state_adjust_rules()
813 ps->performance_levels[i].vddc = max_limits->vddc; in ni_apply_state_adjust_rules()
837 ps->performance_levels[i].vddc = ps->performance_levels[i - 1].vddc; in ni_apply_state_adjust_rules()
875 max_limits->vddc, &ps->performance_levels[i].vddc); in ni_apply_state_adjust_rules()
881 max_limits->vddc, &ps->performance_levels[i].vddc); in ni_apply_state_adjust_rules()
884 max_limits->vddc, &ps->performance_levels[i].vddc); in ni_apply_state_adjust_rules()
1402 &vddc); in ni_calculate_power_boost_limit()
1412 &vddc); in ni_calculate_power_boost_limit()
2365 pl->vddc, &level->vddc); in ni_convert_power_level_to_smc()
3970 pl->vddc = vddc; in ni_parse_pplib_clock_info()
[all …]
H A Drv6xx_dpm.h40 u16 vddc[R600_PM_NUMBER_OF_VOLTAGE_LEVELS]; member
82 u16 vddc; member
H A Drv770_dpm.h65 u16 vddc; member
144 u16 vddc; member
217 int rv770_populate_vddc_value(struct radeon_device *rdev, u16 vddc,
H A Drv730_dpm.c247 &table->ACPIState.levels[0].vddc); in rv730_populate_smc_acpi_state()
254 &table->ACPIState.levels[0].vddc); in rv730_populate_smc_acpi_state()
365 initial_state->low.vddc, in rv730_populate_smc_initial_state()
366 &table->initialState.levels[0].vddc); in rv730_populate_smc_initial_state()
H A Dbtc_dpm.h53 u16 *vddc, u16 *vddci);
H A Dci_dpm.c262 static u8 ci_convert_to_vid(u16 vddc) in ci_convert_to_vid() argument
264 return (6200 - (vddc * VOLTAGE_SCALE)) / 25; in ci_convert_to_vid()
1376 u16 vddc, vddci; in ci_get_leakage_voltages() local
1387 if (vddc != 0 && vddc != virtual_voltage_id) { in ci_get_leakage_voltages()
1388 pi->vddc_leakage.actual_voltage[pi->vddc_leakage.count] = vddc; in ci_get_leakage_voltages()
1399 if (vddc != 0 && vddc != virtual_voltage_id) { in ci_get_leakage_voltages()
4981 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddc = in ci_set_private_data_variables_based_on_pptable()
4996 if (leakage_table->leakage_id[leakage_index] == *vddc) { in ci_patch_with_vddc_leakage()
4997 *vddc = leakage_table->actual_voltage[leakage_index]; in ci_patch_with_vddc_leakage()
5076 ci_patch_with_vddc_leakage(rdev, (u16 *)&table->vddc); in ci_patch_clock_voltage_limits_with_vddc_leakage()
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H A Drv740_dpm.c335 &table->ACPIState.levels[0].vddc); in rv740_populate_smc_acpi_state()
343 &table->ACPIState.levels[0].vddc); in rv740_populate_smc_acpi_state()
H A Drv770_smc.h110 RV770_SMC_VOLTAGE_VALUE vddc; member
H A Dnislands_smc.h110 NISLANDS_SMC_VOLTAGE_VALUE vddc; member
/dragonfly/sys/dev/drm/amd/amdgpu/
H A Dsi_dpm.c2446 state->performance_levels[i-1].vddc, &vddc); in si_populate_power_containment_values()
2455 state->performance_levels[i].vddc, &vddc); in si_populate_power_containment_values()
3400 u16 vddc; in rv770_get_max_vddc() local
3498 if (ps->performance_levels[i].vddc > max_limits->vddc) in si_apply_state_adjust_rules()
3499 ps->performance_levels[i].vddc = max_limits->vddc; in si_apply_state_adjust_rules()
3551 vddc = ps->performance_levels[0].vddc; in si_apply_state_adjust_rules()
3564 ps->performance_levels[0].vddc = vddc; in si_apply_state_adjust_rules()
3575 ps->performance_levels[i].vddc = vddc; in si_apply_state_adjust_rules()
5508 pl->vddc, &level->vddc); in si_convert_power_level_to_smc()
7191 pl->vddc = vddc; in si_parse_pplib_clock_info()
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H A Damdgpu_atombios.h175 u16 *vddc, u16 *vddci,
209 u16 *vddc, u16 *vddci, u16 *mvdd);
H A Dsi_dpm.h441 RV770_SMC_VOLTAGE_VALUE vddc; member
489 u16 vddc; member
601 u16 vddc; member
761 NISLANDS_SMC_VOLTAGE_VALUE vddc; member
H A Damdgpu_dpm.h100 u16 vddc; member
121 u16 vddc; member
/dragonfly/sys/dev/drm/amd/powerplay/hwmgr/
H A Dsmu7_hwmgr.c841 entries[i].vddc = dep_sclk_table->entries[i].vddc; in smu7_odn_initial_default_setting()
853 entries[i].vddc = dep_mclk_table->entries[i].vddc; in smu7_odn_initial_default_setting()
924 if (dep_table->entries[i].vddc != odn_dep_table->entries[i].vddc) { in smu7_check_dpm_table_updated()
933 if (dep_table->entries[i].vddc != odn_dep_table->entries[i].vddc) { in smu7_check_dpm_table_updated()
1767 if (vddc >= 2000 || vddc == 0) in smu7_get_evv_voltages()
1775 if (vddc != 0 && vddc != vv_id) { in smu7_get_evv_voltages()
1836 uint16_t *vddc) in smu7_patch_clock_voltage_limits_with_vddc_leakage() argument
2372 vddc = tab->vddc; in smu7_patch_limits_vddc()
2375 tab->vddc = vddc; in smu7_patch_limits_vddc()
2388 uint32_t vddc; in smu7_patch_cac_vddc() local
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H A Dhwmgr_ppt.h37 uint16_t vddc; member
66 uint16_t vddc; member
H A Dvega10_hwmgr.c333 od_table[2]->entries[i].vddc = odn_table->max_vddc > od_table[2]->entries[i].vddc ? in vega10_odn_initial_default_setting()
335 od_table[2]->entries[i].vddc; in vega10_odn_initial_default_setting()
531 uint32_t vddc = 0; in vega10_get_evv_voltages() local
562 PP_ASSERT_WITH_CODE((vddc < 2000 && vddc != 0), in vega10_get_evv_voltages()
566 if (vddc != 0 && vddc != vv_id) { in vega10_get_evv_voltages()
626 uint16_t *vddc) in vega10_patch_clock_voltage_limits_with_vddc_leakage() argument
659 vdt->entries[entry_id].vddc = in vega10_patch_voltage_dependency_tables_with_lookup_table()
666 mm_table->entries[entry_id].vddc = in vega10_patch_voltage_dependency_tables_with_lookup_table()
1830 uint16_t clk = 0, vddc = 0; in vega10_populate_single_display_type() local
2433 if (dep_table->entries[i].vddc != odn_dep_table->entries[i].vddc) { in vega10_check_dpm_table_updated()
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H A Dsmu_helper.c32 uint8_t convert_to_vid(uint16_t vddc) in convert_to_vid() argument
34 return (uint8_t) ((6200 - (vddc * VOLTAGE_SCALE)) / 25); in convert_to_vid()
510 if (req_vddc <= vddc_table->entries[i].vddc) { in phm_apply_dal_min_voltage_request()
511 req_volt = (((uint32_t)vddc_table->entries[i].vddc) * VOLTAGE_SCALE); in phm_apply_dal_min_voltage_request()
645 dep_table->entries[i].vddc = allowed_dep_table->entries[i].vddc; in smu_get_voltage_dependency_table_ppt_v1()
/dragonfly/sys/dev/drm/amd/powerplay/inc/
H A Dhardwaremanager.h272 uint32_t vddc; member
384 uint32_t vddc; member
/dragonfly/sys/dev/drm/amd/powerplay/smumgr/
H A Dvegam_smumgr.c617 *voltage |= (dep_table->entries[i].vddc * in vegam_get_dependency_volt_by_clk()
627 (dep_table->entries[i].vddc - in vegam_get_dependency_volt_by_clk()
645 *voltage |= (dep_table->entries[i - 1].vddc * VOLTAGE_SCALE) << VDDC_SHIFT; in vegam_get_dependency_volt_by_clk()
655 (dep_table->entries[i - 1].vddc - in vegam_get_dependency_volt_by_clk()
1225 (mm_table->entries[count].vddc * VOLTAGE_SCALE) << VDDC_SHIFT; in vegam_populate_smc_vce_level()
1229 mm_table->entries[count].vddc - VDDC_VDDCI_DELTA); in vegam_populate_smc_vce_level()
1231 vddci = mm_table->entries[count].vddc - VDDC_VDDCI_DELTA; in vegam_populate_smc_vce_level()
1339 (mm_table->entries[count].vddc * VOLTAGE_SCALE) << VDDC_SHIFT; in vegam_populate_smc_uvd_level()
1343 mm_table->entries[count].vddc - VDDC_VDDCI_DELTA); in vegam_populate_smc_uvd_level()
1345 vddci = mm_table->entries[count].vddc - VDDC_VDDCI_DELTA; in vegam_populate_smc_uvd_level()
H A Dfiji_smumgr.c381 *voltage |= (dep_table->entries[i].vddc * in fiji_get_dependency_volt_by_clk()
391 (dep_table->entries[i].vddc - in fiji_get_dependency_volt_by_clk()
409 *voltage |= (dep_table->entries[i - 1].vddc * VOLTAGE_SCALE) << VDDC_SHIFT; in fiji_get_dependency_volt_by_clk()
416 (dep_table->entries[i].vddc - in fiji_get_dependency_volt_by_clk()
1449 (mm_table->entries[count].vddc * VOLTAGE_SCALE) << VDDC_SHIFT; in fiji_populate_smc_vce_level()
1451 ((mm_table->entries[count].vddc - VDDC_VDDCI_DELTA) * in fiji_populate_smc_vce_level()
1486 table->AcpLevel[count].MinVoltage |= (mm_table->entries[count].vddc * in fiji_populate_smc_acp_level()
1488 table->AcpLevel[count].MinVoltage |= ((mm_table->entries[count].vddc - in fiji_populate_smc_acp_level()
1585 table->UvdLevel[count].MinVoltage |= (mm_table->entries[count].vddc * in fiji_populate_smc_uvd_level()
1587 table->UvdLevel[count].MinVoltage |= ((mm_table->entries[count].vddc - in fiji_populate_smc_uvd_level()
H A Dpolaris10_smumgr.c368 *voltage |= (dep_table->entries[i].vddc * in polaris10_get_dependency_volt_by_clk()
378 (dep_table->entries[i].vddc - in polaris10_get_dependency_volt_by_clk()
396 *voltage |= (dep_table->entries[i - 1].vddc * VOLTAGE_SCALE) << VDDC_SHIFT; in polaris10_get_dependency_volt_by_clk()
403 (dep_table->entries[i].vddc - in polaris10_get_dependency_volt_by_clk()
1304 (mm_table->entries[count].vddc * VOLTAGE_SCALE) << VDDC_SHIFT; in polaris10_populate_smc_vce_level()
1308 mm_table->entries[count].vddc - VDDC_VDDCI_DELTA); in polaris10_populate_smc_vce_level()
1310 vddci = mm_table->entries[count].vddc - VDDC_VDDCI_DELTA; in polaris10_populate_smc_vce_level()
1410 table->UvdLevel[count].MinVoltage |= (mm_table->entries[count].vddc * in polaris10_populate_smc_uvd_level()
1415 mm_table->entries[count].vddc - VDDC_VDDCI_DELTA); in polaris10_populate_smc_uvd_level()
1417 vddci = mm_table->entries[count].vddc - VDDC_VDDCI_DELTA; in polaris10_populate_smc_uvd_level()

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