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Searched refs:BW (Results 1 – 25 of 60) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonGenExtract.cpp161 unsigned BW = Ty->getPrimitiveSizeInBits(); in INITIALIZE_PASS_DEPENDENCY() local
162 if (BW != 32 && BW != 64) in INITIALIZE_PASS_DEPENDENCY()
174 APInt A = APInt(BW, ~0ULL).lshr(SR).shl(SL); in INITIALIZE_PASS_DEPENDENCY()
185 uint32_t U = BW - std::max(SL, SR); in INITIALIZE_PASS_DEPENDENCY()
200 APInt C = APInt::getHighBitsSet(BW, BW-U); in INITIALIZE_PASS_DEPENDENCY()
212 Intrinsic::ID IntId = (BW == 32) ? Intrinsic::hexagon_S2_extractu in INITIALIZE_PASS_DEPENDENCY()
H A DHexagonBitTracker.cpp295 uint16_t BW, bool Odd) -> BT::RegisterCell { in evaluate() argument
298 RegisterCell RC = eXTR(Rt, I*BW, I*BW+BW).cat(eXTR(Rs, I*BW, I*BW+BW)); in evaluate()
300 while (I*BW < Ws) { in evaluate()
301 RC.cat(eXTR(Rt, I*BW, I*BW+BW)).cat(eXTR(Rs, I*BW, I*BW+BW)); in evaluate()
H A DHexagonConstPropagation.cpp1589 (void)BW; in evaluateZEXTi()
1629 if (BW <= 64 && Bits != 0) { in evaluateSEXTi()
1654 if (Bits < BW) in evaluateSEXTi()
1766 assert(Bits+Offset <= BW); in evaluateEXTRACTi()
1769 Result = APInt(BW, 0); in evaluateEXTRACTi()
1772 if (BW <= 64) { in evaluateEXTRACTi()
1783 Result = A1.shl(BW-Bits-Offset).ashr(BW-Bits); in evaluateEXTRACTi()
1785 Result = A1.shl(BW-Bits-Offset).lshr(BW-Bits); in evaluateEXTRACTi()
2156 if (Offset >= BW) { in evaluate()
2161 if (Offset+Bits > BW) { in evaluate()
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H A DBitTracker.cpp350 uint16_t BW = getRegBitWidth(RR); in getCell() local
355 return RegisterCell::self(0, BW); in getCell()
362 return RegisterCell::self(0, BW); in getCell()
372 return RegisterCell::top(BW); in getCell()
424 uint16_t BW = A.getBitWidth(); in eIMM() local
425 assert((unsigned)BW == A.getBitWidth() && "BitWidth overflow"); in eIMM()
426 RegisterCell Res(BW); in eIMM()
427 for (uint16_t i = 0; i < BW; ++i) in eIMM()
H A DHexagonExpandCondsets.cpp238 bool isIntReg(RegisterRef RR, unsigned &BW);
1115 bool HexagonExpandCondsets::isIntReg(RegisterRef RR, unsigned &BW) { in isIntReg() argument
1120 BW = 32; in isIntReg()
1124 BW = (RR.Sub != 0) ? 32 : 64; in isIntReg()
H A DHexagonBitSimplify.cpp1363 unsigned BN, BW; in processBlock() local
1364 if (!HBS::getSubregMask(RS, BN, BW, MRI)) in processBlock()
1368 if (!usedBitsEqual(RD, RS) && !HBS::isEqual(DC, 0, SC, BN, BW)) in processBlock()
2182 unsigned BN, BW; in genExtractLow() local
2183 if (!HBS::getSubregMask(RS, BN, BW, MRI)) in genExtractLow()
2185 if (BW < W || !HBS::isEqual(RC, 0, SC, BN, W)) in genExtractLow()
H A DHexagonPatternsHVX.td674 // Do it as (Vu << Vs) | (Vv >> (BW-Vs)).
675 // For Vs == 0 becomes Vu | (Vv >> -BW), since the shift amount is
676 // sign-extended. Then this becomes Vu | (Vv << BW) == Vu.
715 // Do it as (Vu >> -(BW-Vs)) | (Vv >> Vs).
716 // For Vs == 0 becomes (Vu << BW) | Vs == 0 | Vv
/freebsd/contrib/llvm-project/llvm/lib/Transforms/AggressiveInstCombine/
H A DAggressiveInstCombine.cpp840 unsigned BW = DL.getIndexTypeSizeInBits(PtrOp->getType()); in getStrideAndModOffsetOfGEP() local
842 APInt ModOffset(BW, 0); in getStrideAndModOffsetOfGEP()
847 if (!GEP->collectOffset(DL, BW, VarOffsets, ModOffset)) in getStrideAndModOffsetOfGEP()
867 return {APInt(BW, 1), APInt(BW, 0)}; in getStrideAndModOffsetOfGEP()
899 unsigned BW = DL.getIndexTypeSizeInBits(PtrOp->getType()); in foldPatternedLoads() local
907 ConstOffset = APInt(BW, 0); in foldPatternedLoads()
908 Stride = APInt(BW, LA.value()); in foldPatternedLoads()
/freebsd/contrib/llvm-project/llvm/lib/Transforms/Utils/
H A DLibCallsShrinkWrap.cpp445 unsigned BW = I->getOperand(0)->getType()->getPrimitiveSizeInBits(); in generateCondForPow() local
447 if (BW == 8) in generateCondForPow()
449 else if (BW == 16) in generateCondForPow()
451 else if (BW == 32) in generateCondForPow()
/freebsd/contrib/llvm-project/llvm/lib/IR/
H A DConstantRange.cpp742 auto BW = getBitWidth(); in castOp() local
743 APInt Min = APInt::getMinValue(BW); in castOp()
744 APInt Max = APInt::getMaxValue(BW); in castOp()
745 if (ResultBitWidth > BW) { in castOp()
753 auto BW = getBitWidth(); in castOp() local
754 APInt SMin = APInt::getSignedMinValue(BW); in castOp()
755 APInt SMax = APInt::getSignedMaxValue(BW); in castOp()
756 if (ResultBitWidth > BW) { in castOp()
1481 unsigned BW = getBitWidth(); in shl() local
1482 if (RHS->uge(BW)) in shl()
[all …]
/freebsd/contrib/llvm-project/llvm/include/llvm/ADT/
H A DBitVector.h809 BitWord BW = Bits[i]; in applyMask() local
814 if (AddBits) BW |= BitWord(M) << b; in applyMask()
815 else BW &= ~(BitWord(M) << b); in applyMask()
817 Bits[i] = BW; in applyMask()
/freebsd/contrib/llvm-project/llvm/lib/Target/SPIRV/
H A DSPIRVGlobalRegistry.cpp325 unsigned BW = getScalarOrVectorBitWidth(SpvType); in getOrCreateConsIntVector() local
326 return getOrCreateIntCompositeOrNull(Val, I, SpvType, TII, ConstVec, BW, in getOrCreateConsIntVector()
342 unsigned BW = getScalarOrVectorBitWidth(SpvBaseTy); in getOrCreateConsIntArray() local
343 return getOrCreateIntCompositeOrNull(Val, I, SpvType, TII, ConstArr, BW, in getOrCreateConsIntArray()
395 unsigned BW = getScalarOrVectorBitWidth(SpvType); in getOrCreateConsIntVector() local
397 ConstVec, BW, in getOrCreateConsIntVector()
413 unsigned BW = getScalarOrVectorBitWidth(SpvBaseTy); in getOrCreateConsIntArray() local
415 ConstArr, BW, in getOrCreateConsIntArray()
/freebsd/contrib/llvm-project/llvm/lib/Transforms/Scalar/
H A DFloat2Int.cpp173 unsigned BW = I->getOperand(0)->getType()->getPrimitiveSizeInBits(); in walkBackwards() local
174 auto Input = ConstantRange::getFull(BW); in walkBackwards()
H A DConstantHoisting.cpp538 unsigned BW = V1.getBitWidth() > V2.getBitWidth() ? in calculateOffsetDiff() local
547 return APInt(BW, Diff, true); in calculateOffsetDiff()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeVectorOps.cpp1216 unsigned BW = VT.getScalarSizeInBits(); in ExpandSEXTINREG() local
1218 SDValue ShiftSz = DAG.getConstant(BW - OrigBW, DL, VT); in ExpandSEXTINREG()
1617 unsigned BW = VT.getScalarSizeInBits(); in ExpandUINT_TO_FLOAT() local
1618 assert((BW == 64 || BW == 32) && in ExpandUINT_TO_FLOAT()
1621 SDValue HalfWord = DAG.getConstant(BW / 2, DL, VT); in ExpandUINT_TO_FLOAT()
1626 uint64_t HWMask = (BW == 64) ? 0x00000000FFFFFFFF : 0x0000FFFF; in ExpandUINT_TO_FLOAT()
1631 DAG.getConstantFP(1ULL << (BW / 2), DL, Node->getValueType(0)); in ExpandUINT_TO_FLOAT()
/freebsd/contrib/llvm-project/llvm/lib/Transforms/InstCombine/
H A DInstCombineNegator.cpp264 unsigned BW = X->getType()->getScalarSizeInBits(); in visitImpl() local
265 Constant *BWMinusOne = ConstantInt::get(X->getType(), BW - 1); in visitImpl()
/freebsd/contrib/llvm-project/clang/include/clang/AST/
H A DDeclObjC.h1958 QualType T, TypeSourceInfo *TInfo, AccessControl ac, Expr *BW, in ObjCIvarDecl() argument
1960 : FieldDecl(ObjCIvar, DC, StartLoc, IdLoc, Id, T, TInfo, BW, in ObjCIvarDecl()
1969 AccessControl ac, Expr *BW = nullptr,
2029 QualType T, Expr *BW) in ObjCAtDefsFieldDecl() argument
2032 BW, /*Mutable=*/false, /*HasInit=*/ICIS_NoInit) {} in ObjCAtDefsFieldDecl()
2040 QualType T, Expr *BW);
/freebsd/contrib/llvm-project/llvm/lib/Analysis/
H A DBasicAliasAnalysis.cpp1223 unsigned BW = OffsetRange.getBitWidth(); in aliasGEP() local
1225 ConstantRange(APInt(BW, 0), APInt(BW, V1Size.getValue()))); in aliasGEP()
1227 ConstantRange(APInt(BW, 0), APInt(BW, V2Size.getValue())); in aliasGEP()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64SchedTSV110.td444 def : InstRW<[TSV110Wr_4cyc_1LdSt], (instregex "^LDRS(BW|BX|HW|HX|W)ui$")>;
447 def : InstRW<[WriteAdr, TSV110Wr_4cyc_1LdSt], (instregex "^LDRS(BW|BX|HW|HX|W)(post|pre)$")>;
451 def : InstRW<[TSV110Wr_4cyc_1LdSt], (instregex "^LDTRS(BW|BX|HW|HX|W)i$")>;
452 def : InstRW<[TSV110Wr_4cyc_1LdSt], (instregex "^LDURS(BW|BX|HW|HX|W)i$")>;
H A DAArch64SchedFalkorDetails.td1191 (instregex "^LDRS(BW|BX|HW|HX|W)ui$")>;
1193 (instregex "^LDRS(BW|BX|HW|HX|W)(post|pre)$")>;
1195 (instregex "^LDRS(BW|BX|HW|HX|W)ro(W|X)$")>;
1199 (instregex "^LDTRS(BW|BX|HW|HX|W)i$")>;
1201 (instregex "^LDURS(BW|BX|HW|HX|W)i$")>;
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUPromoteAlloca.cpp304 unsigned BW = DL.getIndexTypeSizeInBits(GEP->getType()); in GEPToVectorIndex() local
306 APInt ConstOffset(BW, 0); in GEPToVectorIndex()
308 !GEP->collectOffset(DL, BW, VarOffsets, ConstOffset)) in GEPToVectorIndex()
/freebsd/contrib/llvm-project/clang/lib/AST/
H A DDeclObjC.cpp1843 AccessControl ac, Expr *BW, in Create() argument
1871 return new (C, DC) ObjCIvarDecl(DC, StartLoc, IdLoc, Id, T, TInfo, ac, BW, in Create()
1919 IdentifierInfo *Id, QualType T, Expr *BW) { in Create() argument
1920 return new (C, DC) ObjCAtDefsFieldDecl(DC, StartLoc, IdLoc, Id, T, BW); in Create()
/freebsd/sys/dev/ena/
H A Dena_sysctl.c105 bw_in_allowance_exceeded, Inbound BW allowance exceeded),
107 bw_out_allowance_exceeded, Outbound BW allowance exceeded),
/freebsd/contrib/libdivsufsort/include/
H A Ddivsufsort.h.cmake115 * Inverse BW-transforms a given BWTed string.
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DLegalizerHelper.cpp6212 return !CI || CI->getValue().urem(BW) != 0; in isNonZeroModBitWidthOrUndef()
6223 unsigned BW = Ty.getScalarSizeInBits(); in lowerFunnelShiftWithInverse() local
6225 if (!isPowerOf2_32(BW)) in lowerFunnelShiftWithInverse()
6231 if (isNonZeroModBitWidthOrUndef(MRI, Z, BW)) { in lowerFunnelShiftWithInverse()
6262 const unsigned BW = Ty.getScalarSizeInBits(); in lowerFunnelShiftAsShifts() local
6269 if (isNonZeroModBitWidthOrUndef(MRI, Z, BW)) { in lowerFunnelShiftAsShifts()
6273 auto BitWidthC = MIRBuilder.buildConstant(ShTy, BW); in lowerFunnelShiftAsShifts()
6281 auto Mask = MIRBuilder.buildConstant(ShTy, BW - 1); in lowerFunnelShiftAsShifts()
6282 if (isPowerOf2_32(BW)) { in lowerFunnelShiftAsShifts()
6289 auto BitWidthC = MIRBuilder.buildConstant(ShTy, BW); in lowerFunnelShiftAsShifts()
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