/freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
H A D | SystemZInstrSystem.td | 25 let hasSideEffects = 1, Defs = [CC] in { 33 let Uses = [R2L], Defs = [R2L] in 135 let hasSideEffects = 1, Defs = [CC] in 139 let hasSideEffects = 1, Defs = [CC] in 195 let hasSideEffects = 1, Defs = [CC] in 220 let hasSideEffects = 1, Defs = [CC] in 256 let hasSideEffects = 1, Defs = [CC] in 268 let hasSideEffects = 1, Defs = [CC] in 278 let hasSideEffects = 1, Defs = [CC] in 290 let Defs = [CC] in [all …]
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H A D | SystemZInstrHFP.td | 21 let Defs = [CC] in { 60 let Defs = [CC] in { 71 let Defs = [CC] in { 77 let Defs = [CC] in { 88 let Defs = [CC] in { 95 let Defs = [CC] in { 102 let Defs = [CC] in { 131 let Defs = [CC] in { 142 let Defs = [CC] in { 152 let Defs = [CC] in { [all …]
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H A D | SystemZInstrDFP.td | 22 let Uses = [FPC], Defs = [CC] in { 66 let Uses = [FPC], Defs = [CC] in { 78 let Uses = [FPC], Defs = [CC] in { 116 let Defs = [CC, R1L, F0Q], Uses = [FPC, R0L, F4Q] in 145 let Uses = [FPC], Defs = [CC] in { 157 let Uses = [FPC], Defs = [CC] in { 216 let Uses = [FPC], Defs = [CC] in { 222 let Uses = [FPC], Defs = [CC] in { 228 let Defs = [CC] in { 234 let Defs = [CC] in { [all …]
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H A D | SystemZInstrInfo.td | 137 let Defs = [CC] in { 195 let Defs = [CC] in { 210 let Defs = [CC] in { 898 let Defs = [CC] in { 908 let Defs = [CC] in { 918 let Defs = [CC] in { 943 let Defs = [CC] in { 1195 let Defs = [CC] in { 1781 let Defs = [CC]; 2001 let Defs = [CC] in [all …]
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/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
H A D | SIFormMemoryClauses.cpp | 63 bool canBundle(const MachineInstr &MI, const RegUse &Defs, 67 bool processRegUses(const MachineInstr &MI, RegUse &Defs, RegUse &Uses, 168 const RegUse &Map = MO.isDef() ? Uses : Defs; in canBundle() 228 RegUse &Map = MO.isDef() ? Defs : Uses; in collectRegUses() 245 RegUse &Defs, RegUse &Uses, in processRegUses() argument 247 if (!canBundle(MI, Defs, Uses)) in processRegUses() 253 collectRegUses(MI, Defs, Uses); in processRegUses() 301 RegUse Defs, Uses; in runOnMachineFunction() local 302 if (!processRegUses(MI, Defs, Uses, RPT)) { in runOnMachineFunction() 320 if (!processRegUses(*Next, Defs, Uses, RPT)) in runOnMachineFunction() [all …]
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H A D | SIPostRABundler.cpp | 49 SmallSet<Register, 16> Defs; member in __anoneaa7529c0111::SIPostRABundler 83 for (Register Def : Defs) in isDependentLoad() 152 assert(Defs.empty()); in runOnMachineFunction() 155 Defs.insert(I->defs().begin()->getReg()); in runOnMachineFunction() 167 Defs.insert(I->defs().begin()->getReg()); in runOnMachineFunction() 220 Defs.clear(); in runOnMachineFunction()
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/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
H A D | HexagonGenMux.cpp | 100 BitVector Defs, Uses; member 129 void getDefsUses(const MachineInstr *MI, BitVector &Defs, 164 expandReg(R, Defs); in getDefsUses() 173 BitVector &Set = MO.isDef() ? Defs : Uses; in getDefsUses() 182 BitVector Defs(NR), Uses(NR); in buildMaps() local 186 Defs.reset(); in buildMaps() 188 getDefsUses(&MI, Defs, Uses); in buildMaps() 281 if (!DU.Defs[PR]) in genMuxInBlock() 305 if (DU.Defs[PR] || DU.Defs[DR] || DU.Uses[DR]) { in genMuxInBlock() 309 if (CanDown && DU.Defs[SR1]) in genMuxInBlock() [all …]
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H A D | HexagonPseudo.td | 85 let Defs = [R29, R30, R31], Uses = [R29], isPseudo = 1 in 91 Defs = [PC, LC0], Uses = [SA0, LC0] in { 98 Defs = [PC, LC1], Uses = [SA1, LC1] in { 182 Defs = [PC, R31, R6, R7, P0] in 334 let Defs = [R29], hasSideEffects = 1 in 381 let Defs = [R14, R15, R28, R29, R30, R31, PC] in { 396 let Defs = [R14, R15, R28, R29, R30, R31, PC] in { 411 let Defs = [P0] in 414 let Defs = [P0], isExtended = 1, opExtendable = 0 in 417 let Defs = [R14, R15, R28] in [all …]
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/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
H A D | Thumb2ITBlockPass.cpp | 68 RegisterSet &Defs, RegisterSet &Uses); 81 static void TrackDefUses(MachineInstr *MI, RegisterSet &Defs, RegisterSet &Uses, in INITIALIZE_PASS() 105 InsertUsesDefs(LocalDefs, Defs); in INITIALIZE_PASS() 137 RegisterSet &Defs, RegisterSet &Uses) { in MoveCopyOutOfITBlock() argument 151 if (Uses.count(DstReg) || Defs.count(SrcReg)) in MoveCopyOutOfITBlock() 195 RegisterSet Defs, Uses; in InsertITInstructions() local 208 Defs.clear(); in InsertITInstructions() 210 TrackDefUses(MI, Defs, Uses, TRI); in InsertITInstructions() 252 MoveCopyOutOfITBlock(NMI, CC, OCC, Defs, Uses)) { in InsertITInstructions() 262 TrackDefUses(NMI, Defs, Uses, TRI); in InsertITInstructions()
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/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/ |
H A D | MipsDSPInstrInfo.td | 98 class Defs<list<Register> Regs> { 99 list<Register> Defs = Regs; 557 Defs<[DSPOutFlag20]>; 565 Defs<[DSPOutFlag20]>; 573 Defs<[DSPOutFlag20]>; 581 Defs<[DSPOutFlag20]>; 597 Defs<[DSPCarry]>; 848 Defs<[DSPCCond]>; 852 Defs<[DSPCCond]>; 903 Defs<[DSPOutFlag23]>; [all …]
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H A D | MipsDelaySlotFiller.cpp | 136 BitVector Defs, Uses; member in __anonb48bbe9e0111::RegDefsUses 202 SmallPtrSet<ValueType, 4> Uses, Defs; member in __anonb48bbe9e0111::MemDefsUses 352 Defs.set(Mips::RA); in init() 358 Defs.reset(Mips::AT); in init() 369 Defs.set(Mips::RA); in setCallerSaved() 370 Defs.set(Mips::RA_64); in setCallerSaved() 384 Defs |= CallerSavedRegs; in setCallerSaved() 397 Defs |= AllocSet.flip(); in setUnallocatableRegs() 425 Defs |= NewDefs; in update() 441 return isRegInSet(Defs, Reg); in checkRegDefsUses() [all …]
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H A D | MicroMipsDSPInstrInfo.td | 227 Defs<[DSPOutFlag22]>; 230 Defs<[DSPOutFlag22]>; 233 Defs<[DSPOutFlag22]>; 236 Defs<[DSPOutFlag22]>; 264 Defs<[DSPOutFlag22]>; 299 Defs<[DSPEFI]>; 302 Defs<[DSPPos, DSPEFI]>; 308 Defs<[DSPEFI]>; 310 Defs<[DSPOutFlag23]>; 312 Defs<[DSPOutFlag23]>; [all …]
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/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
H A D | PPCBoolRetToInt.cpp | 74 SmallPtrSet<Value *, 8> Defs; in findAllDefs() local 77 Defs.insert(V); in findAllDefs() 85 if (Defs.insert(Op).second) in findAllDefs() 88 return Defs; in findAllDefs() 221 auto Defs = findAllDefs(U); in runOnUse() local 224 if (llvm::none_of(Defs, [](Value *V) { return isa<Instruction>(V); })) in runOnUse() 230 for (Value *V : Defs) in runOnUse() 235 for (Value *V : Defs) in runOnUse() 246 for (Value *V : Defs) in runOnUse()
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/freebsd/contrib/llvm-project/clang/utils/TableGen/ |
H A D | SveEmitter.cpp | 1222 createIntrinsic(R, Defs); in createCoreHeaderIntrinsics() 1228 std::stable_sort(Defs.begin(), Defs.end(), in createCoreHeaderIntrinsics() 1240 for (auto &I : Defs) in createCoreHeaderIntrinsics() 1437 for (auto &Def : Defs) { in createBuiltins() 1477 for (auto &Def : Defs) { in createCodeGenMap() 1515 for (auto &Def : Defs) { in createRangeChecks() 1635 for (auto &Def : Defs) { in createSMEBuiltins() 1661 for (auto &Def : Defs) { in createSMECodeGenMap() 1700 for (auto &Def : Defs) { in createSMERangeChecks() 1724 for (auto &Def : Defs) { in createBuiltinZAState() [all …]
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H A D | NeonEmitter.cpp | 2020 for (auto *Def : Defs) { in genBuiltinsDef() 2051 for (auto *Def : Defs) { in genStreamingSVECompatibleList() 2087 for (auto *Def : Defs) { in genOverloadTypeCheckCode() 2158 for (auto *Def : Defs) { in genIntrinsicRangeCheckCode() 2248 genBuiltinsDef(OS, Defs); in runHeader() 2411 for (auto *I : Defs) in run() 2449 I = Defs.erase(I); in run() 2520 for (auto *I : Defs) in runFP16() 2558 I = Defs.erase(I); in runFP16() 2629 for (auto *I : Defs) in runBF16() [all …]
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H A D | ClangDataCollectorsEmitter.cpp | 8 const auto &Defs = RK.getClasses(); in EmitClangDataCollectors() local 9 for (const auto &Entry : Defs) { in EmitClangDataCollectors()
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H A D | RISCVVEmitter.cpp | 419 std::vector<std::unique_ptr<RVVIntrinsic>> Defs; in createBuiltins() local 420 createRVVIntrinsics(Defs); in createBuiltins() 429 for (auto &Def : Defs) { in createBuiltins() 450 std::vector<std::unique_ptr<RVVIntrinsic>> Defs; in createCodeGen() local 451 createRVVIntrinsics(Defs); in createCodeGen() 453 llvm::stable_sort(Defs, [](const std::unique_ptr<RVVIntrinsic> &A, in createCodeGen() 465 RVVIntrinsic *PrevDef = Defs.begin()->get(); in createCodeGen() 466 for (auto &Def : Defs) { in createCodeGen() 496 emitCodeGenSwitchBody(Defs.back().get(), OS); in createCodeGen() 747 std::vector<std::unique_ptr<RVVIntrinsic>> Defs; in createSema() local [all …]
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/freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
H A D | X86InstrSNP.td | 19 let Uses = [RAX], Defs = [EAX, EFLAGS] in 24 let Uses = [RAX, RCX, RDX], Defs = [EAX, EFLAGS] in 28 let Uses = [EAX, ECX, EDX], Defs = [EAX, EFLAGS] in 33 let Uses = [RAX, RCX], Defs = [EAX, EFLAGS] in 38 let Uses = [RAX, RCX, RDX], Defs = [EAX, EFLAGS] in 43 let Uses = [RAX, RDX], Defs = [RAX, RCX, RDX, EFLAGS] in
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H A D | X86InstrMisc.td | 436 let Defs = [AL] in 440 let Defs = [AX] in 444 let Defs = [EAX] in 448 let Defs = [RAX] in 453 let Defs = [AL] in 456 let Defs = [AX] in 460 let Defs = [EAX] in 498 let Defs = [AL] in 502 let Defs = [AX] in 506 let Defs = [EAX] in [all …]
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H A D | X86InstrKL.td | 19 let Uses = [XMM0, EAX], Defs = [EFLAGS] in { 25 let Uses = [XMM0], Defs = [XMM0, XMM1, XMM2, XMM4, XMM5, XMM6, EFLAGS] in { 30 let Uses = [XMM0, XMM1], Defs = [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, EFLAGS] in { 36 Defs = [EFLAGS] in { 62 Defs = [EFLAGS, XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7],
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/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
H A D | RISCVInstrInfoZicfiss.td | 28 let Uses = [SSP], Defs = [SSP], hasSideEffects = 0, mayLoad = 1, mayStore = 0 in 33 } // Uses = [SSP], Defs = [SSP], hasSideEffects = 0, mayLoad = 1, mayStore = 0 42 let Uses = [SSP], Defs = [SSP], hasSideEffects = 0, mayLoad = 0, mayStore = 1 in 52 let Uses = [SSP], Defs = [SSP], hasSideEffects = 0, mayLoad = 0, mayStore = 1 in 55 let Uses = [SSP], Defs = [SSP], hasSideEffects = 0, mayLoad = 1, mayStore = 0 in
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/freebsd/contrib/llvm-project/llvm/lib/Analysis/ |
H A D | MemorySSAUpdater.cpp | 151 if (Defs) { in getPreviousDefInBlock() 156 if (Iter != Defs->rend()) in getPreviousDefInBlock() 177 if (Defs) { in getPreviousDefFromEnd() 179 return &*Defs->rbegin(); in getPreviousDefFromEnd() 258 (void)Defs; in insertUse() 259 assert((!Defs || (++Defs->begin() == Defs->end())) && in insertUse() 478 if (++DefIter != Defs->end()) { in fixupDefs() 498 auto *FirstDef = &*Defs->begin(); in fixupDefs() 849 if (Defs) in applyInsertUpdates() 850 return &*(--Defs->end()); in applyInsertUpdates() [all …]
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/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/MCTargetDesc/ |
H A D | HexagonMCChecker.cpp | 47 Defs[Hexagon::LC0].insert(Unconditional); in init() 51 Defs[Hexagon::LC1].insert(Unconditional); in init() 131 Defs[R].insert(PredSense(PredReg, isTrue)); in init() 182 Defs[*SRI].insert(PredSense(PredReg, isTrue)); in init() 390 if (!Defs.count(P) || LatePreds.count(P) || Defs.count(Hexagon::P3_0)) { in checkPredicates() 403 if (LatePreds.count(P) > 1 || Defs.count(P)) { in checkPredicates() 531 for (unsigned j = 0; j < Defs; ++j) { in checkRegistersReadOnly() 609 for (const auto &I : Defs) { in checkRegisters() 612 if (isLoopRegister(R) && Defs.count(R) > 1 && in checkRegisters() 628 if (!HexagonMCInstrInfo::isPredReg(RI, R) && Defs[R].size() > 1) { in checkRegisters() [all …]
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/freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
H A D | LiveVariables.cpp | 472 while (!Defs.empty()) { in UpdatePhysRegDefs() 473 Register Reg = Defs.pop_back_val(); in UpdatePhysRegDefs() 539 HandlePhysRegDef(MOReg, &MI, Defs); in runOnInstr() 541 UpdatePhysRegDefs(MI, Defs); in runOnInstr() 546 SmallVector<unsigned, 4> Defs; in runOnBlock() local 561 runOnInstr(MI, Defs, NumRegs); in runOnBlock() 594 HandlePhysRegDef(i, nullptr, Defs); in runOnBlock() 826 DenseSet<unsigned> Defs, Kills; in addNewBlock() local 831 Defs.insert(BBI->getOperand(0).getReg()); in addNewBlock() 844 Defs.insert(Op.getReg()); in addNewBlock() [all …]
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/freebsd/contrib/llvm-project/llvm/utils/TableGen/ |
H A D | CTagsEmitter.cpp | 70 const auto &Defs = Records.getDefs(); in run() local 73 Tags.reserve(Classes.size() + Defs.size()); in run() 79 for (const auto &D : Defs) in run()
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