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Searched refs:MI (Results 1 – 25 of 1124) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/
H A DCombinerHelper.h52 MachineInstr *MI; member
172 bool tryCombineCopy(MachineInstr &MI);
173 bool matchCombineCopy(MachineInstr &MI);
174 void applyCombineCopy(MachineInstr &MI);
422 bool matchUndefStore(MachineInstr &MI);
491 void eraseInst(MachineInstr &MI);
551 bool matchPtrAddZero(MachineInstr &MI);
552 void applyPtrAddZero(MachineInstr &MI);
588 MachineInstr &MI,
591 MachineInstr &MI,
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H A DLegalizerHelper.h370 LegalizeResult lowerLoad(GAnyLoad &MI);
371 LegalizeResult lowerStore(GStore &MI);
376 LegalizeResult lowerEXT(MachineInstr &MI);
377 LegalizeResult lowerTRUNC(MachineInstr &MI);
379 LegalizeResult lowerRotate(MachineInstr &MI);
382 LegalizeResult lowerUITOFP(MachineInstr &MI);
383 LegalizeResult lowerSITOFP(MachineInstr &MI);
389 LegalizeResult lowerFPOWI(MachineInstr &MI);
396 LegalizeResult lowerFMad(MachineInstr &MI);
414 LegalizeResult lowerBswap(MachineInstr &MI);
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/freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZShortenInst.cpp71 MI.tieOperands(0, 1); in tieOpsIfNeeded()
134 MI.getOperand(1).getReg() == MI.getOperand(0).getReg() && in shortenOn001()
137 tieOpsIfNeeded(MI); in shortenOn001()
147 MachineInstrBuilder(*MI.getParent()->getParent(), &MI) in shortenOn001AddCC()
165 MI.removeOperand(3); in shortenFPConv()
166 MI.removeOperand(2); in shortenFPConv()
167 MI.removeOperand(1); in shortenFPConv()
170 MachineInstrBuilder(*MI.getParent()->getParent(), &MI) in shortenFPConv()
197 MachineInstrBuilder(*MI.getParent()->getParent(), &MI) in shortenFusedFPOp()
359 if ((MI.getOperand(0).getReg() != MI.getOperand(1).getReg()) && in processBlock()
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/freebsd/contrib/llvm-project/llvm/lib/Target/M68k/MCTargetDesc/
H A DM68kInstPrinter.h63 printAbsMem(MI, opNum, O); in printPCRelImm()
67 printARIMem(MI, opNum, O); in printARI8Mem()
70 printARIMem(MI, opNum, O); in printARI16Mem()
73 printARIMem(MI, opNum, O); in printARI32Mem()
97 printARIDMem(MI, opNum, O); in printARID8Mem()
117 printAbsMem(MI, opNum, O); in printAS8Mem()
120 printAbsMem(MI, opNum, O); in printAS16Mem()
123 printAbsMem(MI, opNum, O); in printAS32Mem()
127 printAbsMem(MI, opNum, O); in printAL8Mem()
130 printAbsMem(MI, opNum, O); in printAL16Mem()
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/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonInstrInfo.h72 const MachineInstr &MI,
79 const MachineInstr &MI,
231 bool PredicateInstruction(MachineInstr &MI,
372 bool isFloat(const MachineInstr &MI) const;
377 bool isJumpR(const MachineInstr &MI) const;
380 bool isLoopN(const MachineInstr &MI) const;
401 bool isSolo(const MachineInstr &MI) const;
403 bool isTC1(const MachineInstr &MI) const;
404 bool isTC2(const MachineInstr &MI) const;
406 bool isTC4x(const MachineInstr &MI) const;
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/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DGCNHazardRecognizer.cpp267 BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), TII.get(AMDGPU::S_NOP)) in insertNoopsInBundle()
284 for (; MI != E && MI->isInsideBundle(); ++MI) { in processBundle()
1116 ((TII->isVOP3(MI) || TII->isSDWA(MI)) && MI.isCompare())) && in fixVcmpxPermlaneHazards()
1136 BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), in fixVcmpxPermlaneHazards()
1185 BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), in fixVMEMtoScalarWriteHazards()
1272 BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), in fixSMEMtoVectorWriteHazards()
1315 BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), in fixVcmpxExecWARHazard()
1397 BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), in fixLdsBranchVmemWARHazard()
1481 BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), in fixLdsDirectVMEMHazard()
1631 BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), in fixVALUPartialForwardingHazard()
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H A DSIMemoryLegalizer.cpp787 if (!(MI->mayLoad() && !MI->mayStore())) in getLoadInfo()
801 if (!(!MI->mayLoad() && MI->mayStore())) in getStoreInfo()
848 if (!(MI->mayLoad() && MI->mayStore())) in getAtomicCmpxchgOrRmwInfo()
944 assert(MI->mayLoad() && MI->mayStore()); in enableRMWCacheBypass()
961 assert(MI->mayLoad() ^ MI->mayStore()); in enableVolatileAndOrNonTemporal()
1284 assert(MI->mayLoad() && MI->mayStore()); in enableRMWCacheBypass()
1314 assert(MI->mayLoad() ^ MI->mayStore()); in enableVolatileAndOrNonTemporal()
1616 assert(MI->mayLoad() ^ MI->mayStore()); in enableVolatileAndOrNonTemporal()
1849 assert(MI->mayLoad() ^ MI->mayStore()); in enableVolatileAndOrNonTemporal()
2117 assert(MI->mayLoad() ^ MI->mayStore()); in enableVolatileAndOrNonTemporal()
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H A DSIInstrInfo.h52 void insert(MachineInstr *MI);
71 bool isDeferred(MachineInstr *MI);
425 return isMIMG(MI) || isVSAMPLE(MI) || isVIMAGE(MI); in isImage()
433 return isMUBUF(MI) || isMTBUF(MI) || isImage(MI); in isVMEM()
563 return isVALU(MI) && (isMUBUF(MI) || isFLAT(MI)); in isLDSDMA()
654 if (!isEXP(MI)) in isDualSourceBlendEXP()
692 return isLDSDMA(MI) && MI.getOpcode() != AMDGPU::BUFFER_STORE_LDS_DWORD; in mayWriteLDSThroughDMA()
785 return isMAI(MI) && MI.getOpcode() != AMDGPU::V_ACCVGPR_WRITE_B32_e64 && in isMFMA()
802 return isMFMA(MI) || isWMMA(MI); in isMFMAorWMMA()
952 assert(isCopyInstr(MI)); in isVGPRCopy()
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/freebsd/contrib/llvm-project/llvm/lib/Target/X86/MCTargetDesc/
H A DX86ATTInstPrinter.h77 printSrcIdx(MI, OpNo, O); in printSrcIdx8()
80 printSrcIdx(MI, OpNo, O); in printSrcIdx16()
83 printSrcIdx(MI, OpNo, O); in printSrcIdx32()
86 printSrcIdx(MI, OpNo, O); in printSrcIdx64()
89 printDstIdx(MI, OpNo, O); in printDstIdx8()
92 printDstIdx(MI, OpNo, O); in printDstIdx16()
95 printDstIdx(MI, OpNo, O); in printDstIdx32()
98 printDstIdx(MI, OpNo, O); in printDstIdx64()
101 printMemOffset(MI, OpNo, O); in printMemOffs8()
104 printMemOffset(MI, OpNo, O); in printMemOffs16()
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H A DX86IntelInstPrinter.h88 printSrcIdx(MI, OpNo, O); in printSrcIdx8()
92 printSrcIdx(MI, OpNo, O); in printSrcIdx16()
96 printSrcIdx(MI, OpNo, O); in printSrcIdx32()
100 printSrcIdx(MI, OpNo, O); in printSrcIdx64()
104 printDstIdx(MI, OpNo, O); in printDstIdx8()
108 printDstIdx(MI, OpNo, O); in printDstIdx16()
112 printDstIdx(MI, OpNo, O); in printDstIdx32()
116 printDstIdx(MI, OpNo, O); in printDstIdx64()
120 printMemOffset(MI, OpNo, O); in printMemOffs8()
124 printMemOffset(MI, OpNo, O); in printMemOffs16()
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H A DX86InstComments.cpp287 unsigned NumOperands = MI->getNumOperands(); in printFMAComments()
306 switch (MI->getOpcode()) { in printFMAComments()
618 printMasking(OS, MI, MCII); in printFMAComments()
643 unsigned NumOperands = MI->getNumOperands(); in EmitAnyX86InstComments()
646 if (printFMAComments(MI, OS, MCII)) in EmitAnyX86InstComments()
649 switch (MI->getOpcode()) { in EmitAnyX86InstComments()
1240 if (MI->getOperand(2).isImm() && in EmitAnyX86InstComments()
1241 MI->getOperand(3).isImm()) in EmitAnyX86InstComments()
1250 if (MI->getOperand(3).isImm() && in EmitAnyX86InstComments()
1251 MI->getOperand(4).isImm()) in EmitAnyX86InstComments()
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/freebsd/contrib/llvm-project/llvm/lib/Target/VE/MCTargetDesc/
H A DVEInstPrinter.cpp72 printOperand(MI, OpNum, STI, O); in printMemASXOperand()
86 MI->getOperand(OpNum).isImm() && MI->getOperand(OpNum).getImm() == 0) { in printMemASXOperand()
101 if (MI->getOperand(OpNum).isImm() && MI->getOperand(OpNum).getImm() == 0) { in printMemASXOperand()
116 printOperand(MI, OpNum, STI, O); in printMemASOperandASX()
128 if (MI->getOperand(OpNum).isImm() && MI->getOperand(OpNum).getImm() == 0) { in printMemASOperandASX()
137 printOperand(MI, OpNum, STI, O); in printMemASOperandASX()
147 printOperand(MI, OpNum, STI, O); in printMemASOperandRRM()
159 if (MI->getOperand(OpNum).isImm() && MI->getOperand(OpNum).getImm() == 0) { in printMemASOperandRRM()
168 printOperand(MI, OpNum, STI, O); in printMemASOperandRRM()
178 printOperand(MI, OpNum, STI, O); in printMemASOperandHM()
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/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DMVETailPredUtils.h83 return isDoLoopStart(MI) || isWhileLoopStart(MI); in isLoopStart()
109 BuildMI(*MBB, MI, MI->getDebugLoc(), TII->get(ARM::t2CMPri));
116 BuildMI(*MBB, MI, MI->getDebugLoc(), TII->get(ARM::t2SUBri));
127 BuildMI(*MBB, MI, MI->getDebugLoc(), TII->get(BrOpc));
132 MI->eraseFromParent();
137 BuildMI(*MBB, MI, MI->getDebugLoc(), TII->get(ARM::tMOVr)) in RevertDoLoopStart()
142 MI->eraseFromParent(); in RevertDoLoopStart()
150 BuildMI(*MBB, MI, MI->getDebugLoc(), TII->get(ARM::t2SUBri));
163 MI->eraseFromParent();
174 BuildMI(*MBB, MI, MI->getDebugLoc(), TII->get(ARM::t2CMPri));
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/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/MCTargetDesc/
H A DARMInstPrinter.h34 void printInstruction(const MCInst *MI, uint64_t Address,
55 void printAddrModeTBB(const MCInst *MI, unsigned OpNum,
57 void printAddrModeTBH(const MCInst *MI, unsigned OpNum,
119 printAdrLabelOperand<scale>(MI, OpNum, STI, O); in printAdrLabelOperand()
169 void printCPSIMod(const MCInst *MI, unsigned OpNum,
171 void printCPSIFlag(const MCInst *MI, unsigned OpNum,
214 void printPCLabel(const MCInst *MI, unsigned OpNum,
221 printThumbLdrLabelOperand(MI, OpNum, STI, O); in printThumbLdrLabelOperand()
223 void printFBits16(const MCInst *MI, unsigned OpNum,
225 void printFBits32(const MCInst *MI, unsigned OpNum,
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H A DARMInstPrinter.cpp91 unsigned Opcode = MI->getOpcode(); in printInst()
148 if (MI->getOperand(0).getReg() == ARM::SP && MI->getNumOperands() > 5) { in printInst()
177 if (MI->getOperand(0).getReg() == ARM::SP && MI->getNumOperands() > 5) { in printInst()
245 printRegisterList(MI, 3, STI, O); in printInst()
497 printOperand(MI, Op, STI, O); in printAddrMode2Operand()
571 printOperand(MI, Op, STI, O); in printAddrMode3Operand()
663 printOperand(MI, OpNum, STI, O); in printAddrMode5Operand()
689 printOperand(MI, OpNum, STI, O); in printAddrMode5FP16Operand()
1105 printOperand(MI, Op, STI, O); in printThumbAddrModeRROperand()
1128 printOperand(MI, Op, STI, O); in printThumbAddrModeImm5SOperand()
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/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/MCTargetDesc/
H A DMipsInstPrinter.cpp83 switch (MI->getOpcode()) { in printInst()
93 printSaveRestore(MI, STI, O); in printInst()
98 printSaveRestore(MI, STI, O); in printInst()
103 printSaveRestore(MI, STI, O); in printInst()
108 printSaveRestore(MI, STI, O); in printInst()
119 switch (MI->getOpcode()) { in printInst()
191 printOperand(MI, opNum, STI, O); in printUImm()
203 switch (MI->getOpcode()) { in printMemOperand()
219 printOperand(MI, opNum, STI, O); in printMemOperand()
272 switch (MI.getOpcode()) { in printAlias()
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/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/MCTargetDesc/
H A DAMDGPUInstPrinter.h67 void printCPol(const MCInst *MI, unsigned OpNo,
77 void printFORMAT(const MCInst *MI, unsigned OpNo,
79 void printSymbolicFormat(const MCInst *MI,
105 printOperand(MI, OpNum, STI, O); in printOperand()
134 void printOpSel(const MCInst *MI, unsigned OpNo,
136 void printOpSelHi(const MCInst *MI, unsigned OpNo,
138 void printNegLo(const MCInst *MI, unsigned OpNo,
140 void printNegHi(const MCInst *MI, unsigned OpNo,
177 void printExpSrc0(const MCInst *MI, unsigned OpNo,
179 void printExpSrc1(const MCInst *MI, unsigned OpNo,
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/freebsd/contrib/llvm-project/llvm/lib/Target/Xtensa/MCTargetDesc/
H A DXtensaInstPrinter.cpp165 printOperand(MI, OpNum, O); in printImm8_AsmOperand()
178 printOperand(MI, OpNum, O); in printImm8_sh8_AsmOperand()
189 printOperand(MI, OpNum, O); in printImm12_AsmOperand()
200 printOperand(MI, OpNum, O); in printImm12m_AsmOperand()
210 printOperand(MI, OpNum, O); in printUimm4_AsmOperand()
220 printOperand(MI, OpNum, O); in printUimm5_AsmOperand()
231 printOperand(MI, OpNum, O); in printShimm1_31_AsmOperand()
242 printOperand(MI, OpNum, O); in printImm1_16_AsmOperand()
253 printOperand(MI, OpNum, O); in printOffset8m8_AsmOperand()
264 printOperand(MI, OpNum, O); in printOffset8m16_AsmOperand()
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/freebsd/contrib/llvm-project/llvm/lib/Target/Lanai/MCTargetDesc/
H A DLanaiInstPrinter.cpp42 printOperand(MI, OpNo0, OS); in printInst()
44 printOperand(MI, OpNo1, OS); in printInst()
66 if (MI->getOperand(2).getImm() < 0) in decIncOperator()
75 if (isPreIncrementForm(MI, AddOffset)) { in printMemoryLoadIncrement()
81 if (isPostIncrementForm(MI, AddOffset)) { in printMemoryLoadIncrement()
83 << getRegisterName(MI->getOperand(1).getReg()) << decIncOperator(MI) in printMemoryLoadIncrement()
94 if (isPreIncrementForm(MI, AddOffset)) { in printMemoryStoreIncrement()
103 << decIncOperator(MI) << "]"; in printMemoryStoreIncrement()
110 switch (MI->getOpcode()) { in printAlias()
144 if (!printAlias(MI, OS) && !printAliasInstr(MI, Address, OS)) in printInst()
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/freebsd/contrib/llvm-project/llvm/lib/Target/ARC/
H A DARCBranchFinalize.cpp118 BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), in replaceWithBRcc()
122 .add(MI->getOperand(2)) in replaceWithBRcc()
124 MI->eraseFromParent(); in replaceWithBRcc()
126 replaceWithCmpBcc(MI); in replaceWithBRcc()
133 BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), in replaceWithCmpBcc()
136 .add(MI->getOperand(2)); in replaceWithCmpBcc()
137 BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), TII->get(ARC::Bcc)) in replaceWithCmpBcc()
140 MI->eraseFromParent(); in replaceWithCmpBcc()
156 for (auto &MI : MBB) { in runOnMachineFunction() local
163 if (MI.isBranch()) { in runOnMachineFunction()
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/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/MCTargetDesc/
H A DAArch64InstPrinter.h74 printPostIncOperand(MI, OpNo, Amount, O); in printPostIncOperand()
77 void printVRegOperand(const MCInst *MI, unsigned OpNo,
81 void printAddSubImm(const MCInst *MI, unsigned OpNum,
86 void printShifter(const MCInst *MI, unsigned OpNum,
99 void printMemExtend(const MCInst *MI, unsigned OpNum, in printMemExtend() argument
101 printMemExtend(MI, OpNum, O, SrcRegKind, Width); in printMemExtend()
106 void printCondCode(const MCInst *MI, unsigned OpNum,
120 printUImm12Offset(MI, OpNum, Scale, O); in printUImm12Offset()
126 printAMIndexedWB(MI, OpNum, BitWidth / 8, O); in printAMIndexedWB()
133 void printImmScale(const MCInst *MI, unsigned OpNum,
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H A DAArch64MCCodeEmitter.cpp237 const MCOperand &MO = MI.getOperand(OpIdx); in getLdStUImm12OpValue()
258 const MCOperand &MO = MI.getOperand(OpIdx); in getAdrLabelOpValue()
285 const MCOperand &MO = MI.getOperand(OpIdx); in getAddSubImmOpValue()
320 const MCOperand &MO = MI.getOperand(OpIdx); in getCondBranchTargetOpValue()
342 const MCOperand &MO = MI.getOperand(OpIdx); in getPAuthPCRelOpValue()
365 const MCOperand &MO = MI.getOperand(OpIdx); in getLoadLiteralOpValue()
394 const MCOperand &MO = MI.getOperand(OpIdx); in getMoveWideImmOpValue()
413 const MCOperand &MO = MI.getOperand(OpIdx); in getTestBranchTargetOpValue()
435 const MCOperand &MO = MI.getOperand(OpIdx); in getBranchTargetOpValue()
667 MCOperand UImm16MO = MI.getOperand(1); in fixMOVZ()
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/freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/MCTargetDesc/
H A DCSKYMCCodeEmitter.cpp33 const MCOperand &MO = MI.getOperand(Idx); in getOImmOpValue()
42 const MCOperand &MO = MI.getOperand(Idx); in getImmOpValueIDLY()
53 const MCOperand &MSB = MI.getOperand(Idx); in getImmOpValueMSBSize()
78 .addOperand(MI.getOperand(0)) in expandJBTF()
103 .addOperand(MI.getOperand(0)) in expandNEG()
147 switch (MI.getOpcode()) { in encodeInstruction()
149 TmpInst = MI; in encodeInstruction()
153 expandJBTF(MI, CB, Fixups, STI); in encodeInstruction()
158 expandNEG(MI, CB, Fixups, STI); in encodeInstruction()
163 expandRSUBI(MI, CB, Fixups, STI); in encodeInstruction()
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/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/MCTargetDesc/
H A DPPCInstPrinter.cpp63 (MI->getOpcode() == PPC::ADDIS8 || MI->getOpcode() == PPC::ADDIS) && in printInst()
64 MI->getOperand(2).isExpr()) { in printInst()
65 assert((MI->getOperand(0).isReg() && MI->getOperand(1).isReg()) && in printInst()
74 printOperand(MI, 0, STI, O); in printInst()
76 printOperand(MI, 2, STI, O); in printInst()
78 printOperand(MI, 1, STI, O); in printInst()
87 if (MI->getNumOperands() > 1) { in printInst()
127 printOperand(MI, 0, STI, O); in printInst()
163 if ((MI->getOpcode() == PPC::DCBT || MI->getOpcode() == PPC::DCBTST) && in printInst()
177 printOperand(MI, 1, STI, O); in printInst()
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/freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/MCTargetDesc/
H A DSystemZInstPrinter.cpp80 printInstruction(MI, Address, O); in printInst()
112 printUImmOperand<1>(MI, OpNum, O); in printU1ImmOperand()
117 printUImmOperand<2>(MI, OpNum, O); in printU2ImmOperand()
122 printUImmOperand<3>(MI, OpNum, O); in printU3ImmOperand()
127 printUImmOperand<4>(MI, OpNum, O); in printU4ImmOperand()
132 printSImmOperand<8>(MI, OpNum, O); in printS8ImmOperand()
137 printUImmOperand<8>(MI, OpNum, O); in printU8ImmOperand()
185 printPCRelOperand(MI, OpNum, O); in printPCRelTLSOperand()
212 printAddress(&MAI, MI->getOperand(OpNum).getReg(), MI->getOperand(OpNum + 1), in printBDAddrOperand()
218 printAddress(&MAI, MI->getOperand(OpNum).getReg(), MI->getOperand(OpNum + 1), in printBDXAddrOperand()
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