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Searched refs:MLX5_ST_SZ_DW (Results 1 – 25 of 44) sorted by relevance

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/freebsd/sys/dev/mlx5/mlx5_core/
H A Dmlx5_transobj.c66 u32 out[MLX5_ST_SZ_DW(create_rq_out)] = {0}; in mlx5_core_create_rq()
80 u32 out[MLX5_ST_SZ_DW(modify_rq_out)] = {0}; in mlx5_core_modify_rq()
89 u32 in[MLX5_ST_SZ_DW(destroy_rq_in)] = {0}; in mlx5_core_destroy_rq()
90 u32 out[MLX5_ST_SZ_DW(destroy_rq_out)] = {0}; in mlx5_core_destroy_rq()
100 u32 in[MLX5_ST_SZ_DW(query_rq_in)] = {0}; in mlx5_core_query_rq()
111 u32 out[MLX5_ST_SZ_DW(create_sq_out)] = {0}; in mlx5_core_create_sq()
125 u32 out[MLX5_ST_SZ_DW(modify_sq_out)] = {0}; in mlx5_core_modify_sq()
134 u32 in[MLX5_ST_SZ_DW(destroy_sq_in)] = {0}; in mlx5_core_destroy_sq()
145 u32 in[MLX5_ST_SZ_DW(query_sq_in)] = {0}; in mlx5_core_query_sq()
171 u32 in[MLX5_ST_SZ_DW(destroy_tir_in)] = {0}; in mlx5_core_destroy_tir()
[all …]
H A Dmlx5_port.c73 u32 in[MLX5_ST_SZ_DW(qcam_reg)] = {}; in mlx5_query_qcam_reg()
149 u32 in[MLX5_ST_SZ_DW(ptys_reg)]; in mlx5_query_port_ptys()
166 u32 out[MLX5_ST_SZ_DW(ptys_reg)]; in mlx5_query_port_proto_cap()
185 u32 out[MLX5_ST_SZ_DW(ptys_reg)]; in mlx5_query_port_autoneg()
230 u32 out[MLX5_ST_SZ_DW(ptys_reg)]; in mlx5_query_port_proto_admin()
249 u32 out[MLX5_ST_SZ_DW(ptys_reg)]; in mlx5_query_port_eth_proto_oper()
325 u32 out[MLX5_ST_SZ_DW(paos_reg)]; in mlx5_query_port_admin_status()
429 u32 out[MLX5_ST_SZ_DW(pfcc_reg)]; in mlx5_query_port_pfc()
842 u32 in[MLX5_ST_SZ_DW(qetc_reg)]; in mlx5_query_port_qetcr_reg()
863 u32 out[MLX5_ST_SZ_DW(qetc_reg)]; in mlx5_set_port_qetcr_reg()
[all …]
H A Dmlx5_fw.c36 u32 in[MLX5_ST_SZ_DW(query_adapter_in)]; in mlx5_cmd_query_adapter()
252 u32 in[MLX5_ST_SZ_DW(init_hca_in)]; in mlx5_cmd_init_hca()
253 u32 out[MLX5_ST_SZ_DW(init_hca_out)]; in mlx5_cmd_init_hca()
378 u32 out[MLX5_ST_SZ_DW(mcc_reg)]; in mlx5_reg_mcc_set()
379 u32 in[MLX5_ST_SZ_DW(mcc_reg)]; in mlx5_reg_mcc_set()
396 u32 out[MLX5_ST_SZ_DW(mcc_reg)]; in mlx5_reg_mcc_query()
397 u32 in[MLX5_ST_SZ_DW(mcc_reg)]; in mlx5_reg_mcc_query()
423 u32 out[MLX5_ST_SZ_DW(mcda_reg)]; in mlx5_reg_mcda_set()
454 u32 out[MLX5_ST_SZ_DW(mcqi_reg) + MLX5_ST_SZ_DW(mcqi_cap)]; in mlx5_reg_mcqi_query()
455 int offset = MLX5_ST_SZ_DW(mcqi_reg); in mlx5_reg_mcqi_query()
[all …]
H A Dmlx5_fs_cmd.c42 u32 in[MLX5_ST_SZ_DW(set_flow_table_root_in)] = {0}; in mlx5_cmd_update_root_ft()
43 u32 out[MLX5_ST_SZ_DW(set_flow_table_root_out)] = {0}; in mlx5_cmd_update_root_ft()
60 u32 in[MLX5_ST_SZ_DW(create_flow_table_in)] = {0}; in mlx5_cmd_fs_create_ft()
61 u32 out[MLX5_ST_SZ_DW(create_flow_table_out)] = {0}; in mlx5_cmd_fs_create_ft()
93 u32 in[MLX5_ST_SZ_DW(destroy_flow_table_in)] = {0}; in mlx5_cmd_fs_destroy_ft()
94 u32 out[MLX5_ST_SZ_DW(destroy_flow_table_out)] = {0}; in mlx5_cmd_fs_destroy_ft()
117 u32 out[MLX5_ST_SZ_DW(create_flow_group_out)] = {0}; in mlx5_cmd_fs_create_fg()
144 u32 in[MLX5_ST_SZ_DW(destroy_flow_group_in)] = {0}; in mlx5_cmd_fs_destroy_fg()
173 u32 out[MLX5_ST_SZ_DW(set_fte_out)] = {0}; in mlx5_cmd_fs_set_fte()
299 u32 in[MLX5_ST_SZ_DW(delete_fte_in)] = {0}; in mlx5_cmd_fs_delete_fte()
[all …]
H A Dmlx5_qp.c123 u32 out[MLX5_ST_SZ_DW(create_qp_out)] = {0}; in mlx5_core_create_qp()
124 u32 dout[MLX5_ST_SZ_DW(destroy_qp_out)] = {0}; in mlx5_core_create_qp()
125 u32 din[MLX5_ST_SZ_DW(destroy_qp_in)] = {0}; in mlx5_core_create_qp()
158 u32 out[MLX5_ST_SZ_DW(destroy_qp_out)] = {0}; in mlx5_core_destroy_qp()
159 u32 in[MLX5_ST_SZ_DW(destroy_qp_in)] = {0}; in mlx5_core_destroy_qp()
324 u32 in[MLX5_ST_SZ_DW(query_qp_in)] = {0}; in mlx5_core_qp_query()
335 u32 in[MLX5_ST_SZ_DW(alloc_xrcd_in)] = {0}; in mlx5_core_xrcd_alloc()
408 u32 out[MLX5_ST_SZ_DW(drain_dct_out)] = {0}; in mlx5_core_drain_dct()
461 u32 in[MLX5_ST_SZ_DW(query_dct_in)] = {0}; in mlx5_core_dct_query()
473 u32 out[MLX5_ST_SZ_DW(arm_dct_out)] = {0}; in mlx5_core_arm_dct()
[all …]
H A Dmlx5_mr.c60 u32 lout[MLX5_ST_SZ_DW(create_mkey_out)] = {0}; in mlx5_core_create_mkey_cb()
126 u32 out[MLX5_ST_SZ_DW(destroy_mkey_out)] = {0}; in mlx5_core_destroy_mkey()
127 u32 in[MLX5_ST_SZ_DW(destroy_mkey_in)] = {0}; in mlx5_core_destroy_mkey()
149 u32 in[MLX5_ST_SZ_DW(query_mkey_in)] = {0}; in mlx5_core_query_mkey()
162 u32 out[MLX5_ST_SZ_DW(query_special_contexts_out)] = {0}; in mlx5_core_dump_fill_mkey()
163 u32 in[MLX5_ST_SZ_DW(query_special_contexts_in)] = {0}; in mlx5_core_dump_fill_mkey()
189 u32 out[MLX5_ST_SZ_DW(create_psv_out)] = {0}; in mlx5_core_create_psv()
190 u32 in[MLX5_ST_SZ_DW(create_psv_in)] = {0}; in mlx5_core_create_psv()
214 u32 out[MLX5_ST_SZ_DW(destroy_psv_out)] = {0}; in mlx5_core_destroy_psv()
215 u32 in[MLX5_ST_SZ_DW(destroy_psv_in)] = {0}; in mlx5_core_destroy_psv()
H A Dmlx5_fc_cmd.c38 u32 out[MLX5_ST_SZ_DW(alloc_flow_counter_out)] = {}; in mlx5_cmd_fc_bulk_alloc()
39 u32 in[MLX5_ST_SZ_DW(alloc_flow_counter_in)] = {}; in mlx5_cmd_fc_bulk_alloc()
59 u32 in[MLX5_ST_SZ_DW(dealloc_flow_counter_in)] = {}; in mlx5_cmd_fc_free()
72 u32 in[MLX5_ST_SZ_DW(query_flow_counter_in)] = {}; in mlx5_cmd_fc_query()
94 u32 in[MLX5_ST_SZ_DW(query_flow_counter_in)] = {}; in mlx5_cmd_fc_bulk_query()
H A Dmlx5_mcg.c37 u32 in[MLX5_ST_SZ_DW(attach_to_mcg_in)] = {0}; in mlx5_core_attach_mcg()
38 u32 out[MLX5_ST_SZ_DW(attach_to_mcg_out)] = {0}; in mlx5_core_attach_mcg()
51 u32 in[MLX5_ST_SZ_DW(detach_from_mcg_in)] = {0}; in mlx5_core_detach_mcg()
52 u32 out[MLX5_ST_SZ_DW(detach_from_mcg_out)] = {0}; in mlx5_core_detach_mcg()
H A Dmlx5_pd.c36 u32 in[MLX5_ST_SZ_DW(alloc_pd_in)] = {0}; in mlx5_core_alloc_pd()
37 u32 out[MLX5_ST_SZ_DW(alloc_pd_out)] = {0}; in mlx5_core_alloc_pd()
54 u32 in[MLX5_ST_SZ_DW(dealloc_pd_in)] = {0}; in mlx5_core_dealloc_pd()
55 u32 out[MLX5_ST_SZ_DW(dealloc_pd_out)] = {0}; in mlx5_core_dealloc_pd()
H A Dmlx5_tls.c39 u32 in[MLX5_ST_SZ_DW(create_encryption_key_in)] = {}; in mlx5_encryption_key_create()
40 u32 out[MLX5_ST_SZ_DW(create_encryption_key_out)] = {}; in mlx5_encryption_key_create()
86 u32 in[MLX5_ST_SZ_DW(destroy_encryption_key_in)] = {}; in mlx5_encryption_key_destroy()
87 u32 out[MLX5_ST_SZ_DW(destroy_encryption_key_out)] = {}; in mlx5_encryption_key_destroy()
98 u32 in[MLX5_ST_SZ_DW(create_tis_in)] = {}; in mlx5_tls_open_tis()
124 u32 in[MLX5_ST_SZ_DW(create_tir_in)] = {}; in mlx5_tls_open_tir()
H A Dmlx5_mpfs.c48 u32 in[MLX5_ST_SZ_DW(set_l2_table_entry_in)] = {}; in mlx5_mpfs_add_mac()
49 u32 out[MLX5_ST_SZ_DW(set_l2_table_entry_out)] = {}; in mlx5_mpfs_add_mac()
90 u32 in[MLX5_ST_SZ_DW(delete_l2_table_entry_in)] = {}; in mlx5_mpfs_del_mac()
91 u32 out[MLX5_ST_SZ_DW(delete_l2_table_entry_out)] = {}; in mlx5_mpfs_del_mac()
H A Dmlx5_cq.c129 u32 din[MLX5_ST_SZ_DW(destroy_cq_in)] = {0}; in mlx5_core_create_cq()
130 u32 dout[MLX5_ST_SZ_DW(destroy_cq_out)] = {0}; in mlx5_core_create_cq()
168 u32 out[MLX5_ST_SZ_DW(destroy_cq_out)] = {0}; in mlx5_core_destroy_cq()
169 u32 in[MLX5_ST_SZ_DW(destroy_cq_in)] = {0}; in mlx5_core_destroy_cq()
195 u32 in[MLX5_ST_SZ_DW(query_cq_in)] = {0}; in mlx5_core_query_cq()
208 u32 out[MLX5_ST_SZ_DW(modify_cq_out)] = {0}; in mlx5_core_modify_cq()
241 u32 in[MLX5_ST_SZ_DW(modify_cq_in)] = {}; in mlx5_core_modify_cq_by_mask()
H A Dmlx5_vport.c41 u32 in[MLX5_ST_SZ_DW(query_vport_state_in)] = {0}; in _mlx5_query_vport_state()
59 u32 out[MLX5_ST_SZ_DW(query_vport_state_out)] = {0}; in mlx5_query_vport_state()
69 u32 out[MLX5_ST_SZ_DW(query_vport_state_out)] = {0}; in mlx5_query_vport_admin_state()
80 u32 in[MLX5_ST_SZ_DW(modify_vport_state_in)] = {0}; in mlx5_modify_vport_admin_state()
81 u32 out[MLX5_ST_SZ_DW(modify_vport_state_out)] = {0}; in mlx5_modify_vport_admin_state()
135 u32 in[MLX5_ST_SZ_DW(alloc_q_counter_in)] = {0}; in mlx5_vport_alloc_q_counter()
136 u32 out[MLX5_ST_SZ_DW(alloc_q_counter_out)] = {0}; in mlx5_vport_alloc_q_counter()
160 u32 in[MLX5_ST_SZ_DW(dealloc_q_counter_in)] = {0}; in mlx5_vport_dealloc_q_counter()
161 u32 out[MLX5_ST_SZ_DW(dealloc_q_counter_out)] = {0}; in mlx5_vport_dealloc_q_counter()
185 u32 in[MLX5_ST_SZ_DW(query_q_counter_in)] = {0}; in mlx5_vport_query_q_counter()
[all …]
H A Dmlx5_rl.c62 u32 in[MLX5_ST_SZ_DW(set_rate_limit_in)] = {}; in mlx5_set_rate_limit_cmd()
63 u32 out[MLX5_ST_SZ_DW(set_rate_limit_out)] = {}; in mlx5_set_rate_limit_cmd()
78 u32 in[MLX5_ST_SZ_DW(query_pp_rate_limit_in)] = {}; in mlx5e_query_rate_limit_cmd()
79 u32 out[MLX5_ST_SZ_DW(query_pp_rate_limit_out)] = {}; in mlx5e_query_rate_limit_cmd()
H A Dmlx5_srq.c286 u32 create_out[MLX5_ST_SZ_DW(create_srq_out)] = {0}; in create_srq_cmd()
318 u32 srq_out[MLX5_ST_SZ_DW(destroy_srq_out)] = {0}; in destroy_srq_cmd()
319 u32 srq_in[MLX5_ST_SZ_DW(destroy_srq_in)] = {0}; in destroy_srq_cmd()
330 u32 srq_in[MLX5_ST_SZ_DW(query_srq_in)] = {0}; in query_srq_cmd()
359 u32 srq_in[MLX5_ST_SZ_DW(arm_xrc_srq_in)] = {0}; in arm_srq_cmd()
360 u32 srq_out[MLX5_ST_SZ_DW(arm_xrc_srq_out)] = {0}; in arm_srq_cmd()
H A Dmlx5_uar.c37 u32 out[MLX5_ST_SZ_DW(alloc_uar_out)] = {0}; in mlx5_cmd_alloc_uar()
38 u32 in[MLX5_ST_SZ_DW(alloc_uar_in)] = {0}; in mlx5_cmd_alloc_uar()
51 u32 out[MLX5_ST_SZ_DW(dealloc_uar_out)] = {0}; in mlx5_cmd_free_uar()
52 u32 in[MLX5_ST_SZ_DW(dealloc_uar_in)] = {0}; in mlx5_cmd_free_uar()
H A Dflow_table.h37 u32 match_criteria[MLX5_ST_SZ_DW(fte_match_param)];
H A Dmlx5_pagealloc.c300 u32 in[MLX5_ST_SZ_DW(query_pages_in)] = {0}; in mlx5_cmd_query_pages()
301 u32 out[MLX5_ST_SZ_DW(query_pages_out)] = {0}; in mlx5_cmd_query_pages()
322 u32 out[MLX5_ST_SZ_DW(manage_pages_out)] = {0}; in give_pages()
420 u32 in[MLX5_ST_SZ_DW(manage_pages_in)] = {0}; in reclaim_pages()
H A Dmlx5_eq.c90 u32 in[MLX5_ST_SZ_DW(destroy_eq_in)] = {0}; in mlx5_cmd_destroy_eq()
91 u32 out[MLX5_ST_SZ_DW(destroy_eq_out)] = {0}; in mlx5_cmd_destroy_eq()
427 u32 out[MLX5_ST_SZ_DW(create_eq_out)] = {0}; in mlx5_create_map_eq()
632 u32 in[MLX5_ST_SZ_DW(query_eq_in)] = {0}; in mlx5_core_eq_query()
H A Dmlx5_main.c269 u32 in[MLX5_ST_SZ_DW(mpein_reg)] = {}; in mlx5_pci_read_power_status()
270 u32 out[MLX5_ST_SZ_DW(mpein_reg)] = {}; in mlx5_pci_read_power_status()
468 u32 out[MLX5_ST_SZ_DW(set_hca_cap_out)] = {0}; in set_caps()
611 u32 out[MLX5_ST_SZ_DW(enable_hca_out)] = {0}; in mlx5_core_enable_hca()
612 u32 in[MLX5_ST_SZ_DW(enable_hca_in)] = {0}; in mlx5_core_enable_hca()
621 u32 out[MLX5_ST_SZ_DW(disable_hca_out)] = {0}; in mlx5_core_disable_hca()
622 u32 in[MLX5_ST_SZ_DW(disable_hca_in)] = {0}; in mlx5_core_disable_hca()
630 u32 query_in[MLX5_ST_SZ_DW(query_issi_in)] = {0}; in mlx5_core_set_issi()
631 u32 query_out[MLX5_ST_SZ_DW(query_issi_out)] = {0}; in mlx5_core_set_issi()
655 u32 set_in[MLX5_ST_SZ_DW(set_issi_in)] = {0}; in mlx5_core_set_issi()
[all …]
/freebsd/sys/dev/mlx5/mlx5_fpga/
H A Dmlx5fpga_cmd.c75 u32 in[MLX5_ST_SZ_DW(fpga_cap)] = {0}; in mlx5_fpga_caps()
84 u32 in[MLX5_ST_SZ_DW(fpga_ctrl)] = {0}; in mlx5_fpga_ctrl_op()
85 u32 out[MLX5_ST_SZ_DW(fpga_ctrl)]; in mlx5_fpga_ctrl_op()
128 u32 in[MLX5_ST_SZ_DW(fpga_ctrl)] = {0}; in mlx5_fpga_ctrl_write()
129 u32 out[MLX5_ST_SZ_DW(fpga_ctrl)]; in mlx5_fpga_ctrl_write()
151 u32 in[MLX5_ST_SZ_DW(fpga_ctrl)] = {0}; in mlx5_fpga_query()
152 u32 out[MLX5_ST_SZ_DW(fpga_ctrl)]; in mlx5_fpga_query()
169 u32 in[MLX5_ST_SZ_DW(fpga_ctrl)] = {0}; in mlx5_fpga_ctrl_connect()
170 u32 out[MLX5_ST_SZ_DW(fpga_ctrl)]; in mlx5_fpga_ctrl_connect()
196 u32 in[MLX5_ST_SZ_DW(mtmp_reg)] = {0}; in mlx5_fpga_query_mtmp()
[all …]
H A Dconn.h50 u32 fpga_qpc[MLX5_ST_SZ_DW(fpga_qpc)];
/freebsd/sys/dev/mlx5/
H A Dfs.h81 u32 match_criteria[MLX5_ST_SZ_DW(fte_match_param)];
82 u32 match_value[MLX5_ST_SZ_DW(fte_match_param)];
239 u32 match_criteria[MLX5_ST_SZ_DW(fte_match_param)];
240 u32 match_value[MLX5_ST_SZ_DW(fte_match_param)];
246 u32 match_criteria[MLX5_ST_SZ_DW(fte_match_param)];
/freebsd/sys/dev/mlx5/mlx5_lib/
H A Dmlx5_gid.c126 u32 in[MLX5_ST_SZ_DW(set_roce_address_in)] = {0}; in mlx5_core_roce_gid_set()
127 u32 out[MLX5_ST_SZ_DW(set_roce_address_out)] = {0}; in mlx5_core_roce_gid_set()
/freebsd/sys/dev/mlx5/mlx5_fpga_tools/
H A Dmlx5fpga_tools_char.c192 CTASSERT(MLX5_FPGA_CAP_ARR_SZ == MLX5_ST_SZ_DW(fpga_cap));
203 u32 fpga_cap[MLX5_ST_SZ_DW(fpga_cap)] = {0}; in tools_char_ioctl()

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