/freebsd/contrib/llvm-project/llvm/tools/llvm-mca/Views/ |
H A D | ResourcePressureView.cpp | 29 const MCProcResourceDesc &ProcResource = *SM.getProcResource(I); in ResourcePressureView() local 30 unsigned NumUnits = ProcResource.NumUnits; in ResourcePressureView() 32 if (ProcResource.SubUnitsIdxBegin || !NumUnits) in ResourcePressureView() 36 R2VIndex += ProcResource.NumUnits; in ResourcePressureView() 73 const MCProcResourceDesc &ProcResource = *SM.getProcResource(I); in printColumnNames() local 74 unsigned NumUnits = ProcResource.NumUnits; in printColumnNames() 76 if (ProcResource.SubUnitsIdxBegin || !NumUnits) in printColumnNames() 112 const MCProcResourceDesc &ProcResource = *SM.getProcResource(I); in printResourcePressurePerIter() local 113 unsigned NumUnits = ProcResource.NumUnits; in printResourcePressurePerIter() 115 if (ProcResource.SubUnitsIdxBegin || !NumUnits) in printResourcePressurePerIter() [all …]
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H A D | SchedulerStatistics.cpp | 141 const MCProcResourceDesc &ProcResource = *SM.getProcResource(I); in printSchedulerUsage() local 142 if (ProcResource.BufferSize <= 0) in printSchedulerUsage() 147 double AlmostFullThreshold = (double)(ProcResource.BufferSize * 4) / 5; in printSchedulerUsage() 151 FOS << ProcResource.Name; in printSchedulerUsage() 160 BU.MaxUsedSlots == static_cast<unsigned>(ProcResource.BufferSize)) in printSchedulerUsage() 166 FOS << ProcResource.BufferSize << '\n'; in printSchedulerUsage()
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/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
H A D | AArch64SchedFalkor.td | 39 def FalkorUnitB : ProcResource<1>; // Branch 40 def FalkorUnitLD : ProcResource<1>; // Load pipe 41 def FalkorUnitSD : ProcResource<1>; // Store data 42 def FalkorUnitST : ProcResource<1>; // Store pipe 44 def FalkorUnitY : ProcResource<1>; // Simple arithmetic 45 def FalkorUnitZ : ProcResource<1>; // Simple arithmetic 47 def FalkorUnitVSD : ProcResource<1>; // Vector store data 48 def FalkorUnitVX : ProcResource<1>; // Vector X-pipe 49 def FalkorUnitVY : ProcResource<1>; // Vector Y-pipe 51 def FalkorUnitGTOV : ProcResource<1>; // Scalar to Vector [all …]
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H A D | AArch64SchedExynosM5.td | 38 def M5UnitA : ProcResource<2>; // Simple integer 44 def M5UnitF : ProcResource<2>; // CRC (inside C) 45 def M5UnitB : ProcResource<1>; // Branch 46 def M5UnitL0 : ProcResource<1>; // Load 47 def M5UnitS0 : ProcResource<1>; // Store 48 def M5PipeLS : ProcResource<1>; // Load/Store 50 def M5UnitL1 : ProcResource<1>; 51 def M5UnitS1 : ProcResource<1>; 53 def M5PipeF0 : ProcResource<1>; // FP #0 66 def M5PipeF1 : ProcResource<1>; // FP #1 [all …]
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H A D | AArch64SchedExynosM3.td | 39 def M3UnitA : ProcResource<2>; // Simple integer 42 def M3UnitB : ProcResource<2>; // Branch 43 def M3UnitL : ProcResource<2>; // Load 44 def M3UnitS : ProcResource<1>; // Store 45 def M3PipeF0 : ProcResource<1>; // FP #0 48 def M3UnitFADD0 : ProcResource<1>; // Simple FP 56 def M3PipeF1 : ProcResource<1>; // FP #1 59 def M3UnitFADD1 : ProcResource<1>; // Simple FP 62 def M3UnitFST0 : ProcResource<1>; // FP store 69 def M3PipeF2 : ProcResource<1>; // FP #2 [all …]
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H A D | AArch64SchedExynosM4.td | 38 def M4UnitA : ProcResource<2>; // Simple integer 44 def M4UnitB : ProcResource<2>; // Branch 45 def M4UnitL0 : ProcResource<1>; // Load 46 def M4UnitS0 : ProcResource<1>; // Store 47 def M4PipeLS : ProcResource<1>; // Load/Store 49 def M4UnitL1 : ProcResource<1>; 50 def M4UnitS1 : ProcResource<1>; 52 def M4PipeF0 : ProcResource<1>; // FP #0 65 def M4PipeF1 : ProcResource<1>; // FP #1 71 def M4UnitFST0 : ProcResource<1>; // FP store [all …]
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H A D | AArch64SchedKryo.td | 42 def KryoUnitXA : ProcResource<1>; // Type X(A) micro-ops 43 def KryoUnitXB : ProcResource<1>; // Type X(B) micro-ops 44 def KryoUnitYA : ProcResource<1>; // Type Y(A) micro-ops 45 def KryoUnitYB : ProcResource<1>; // Type Y(B) micro-ops 54 def KryoUnitLSA : ProcResource<1>; // Type LS(A) micro-ops 55 def KryoUnitLSB : ProcResource<1>; // Type LS(B) micro-ops
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H A D | AArch64SchedA53.td | 39 // Modeling each pipeline as a ProcResource using the BufferSize = 0 since 42 def A53UnitALU : ProcResource<2> { let BufferSize = 0; } // Int ALU 43 def A53UnitMAC : ProcResource<1> { let BufferSize = 0; } // Int MAC 44 def A53UnitDiv : ProcResource<1> { let BufferSize = 0; } // Int Division 45 def A53UnitLdSt : ProcResource<1> { let BufferSize = 0; } // Load/Store 46 def A53UnitB : ProcResource<1> { let BufferSize = 0; } // Branch 47 def A53UnitFPALU : ProcResource<1> { let BufferSize = 0; } // FP ALU 48 def A53UnitFPMDS : ProcResource<1> { let BufferSize = 0; } // FP Mult/Div/Sqrt
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H A D | AArch64SchedThunderX.td | 37 def THXT8XUnitALU : ProcResource<2> { let BufferSize = 0; } // Int ALU 38 def THXT8XUnitMAC : ProcResource<1> { let BufferSize = 0; } // Int MAC 39 def THXT8XUnitDiv : ProcResource<1> { let BufferSize = 0; } // Int Division 40 def THXT8XUnitLdSt : ProcResource<1> { let BufferSize = 0; } // Load/Store 41 def THXT8XUnitBr : ProcResource<1> { let BufferSize = 0; } // Branch 42 def THXT8XUnitFPALU : ProcResource<1> { let BufferSize = 0; } // FP ALU 43 def THXT8XUnitFPMDS : ProcResource<1> { let BufferSize = 0; } // FP Mul/Div/Sqrt
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/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
H A D | PPCScheduleP9.td | 89 def ALU : ProcResource<4>; 90 def ALUE : ProcResource<2> { 100 def DIV : ProcResource<2>; 103 def DP : ProcResource<4>; 104 def DPE : ProcResource<2> { 108 def DPO : ProcResource<2> { 114 def LS : ProcResource<4>; 117 def PM : ProcResource<2>; 120 def DFU : ProcResource<1>; 123 def BR : ProcResource<1> { [all …]
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H A D | PPCScheduleP8.td | 30 def P8_LU_LS_FX : ProcResource<6>; 35 def P8_DFU : ProcResource<1>; 37 def P8_CY : ProcResource<1>; 38 def P8_CRL : ProcResource<1>; 39 def P8_VMX : ProcResource<2>; 40 def P8_PM : ProcResource<2> { 47 def P8_FPU : ProcResource<4>; 64 def P8_PORT_ALLFX : ProcResource<6>; 73 def P8_PORT_VMX_FP : ProcResource<2>; 75 def P8_PORT_BR : ProcResource<1>; [all …]
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H A D | PPCScheduleP10.td | 42 def P10_BF : ProcResource<4>; // Four Binary Floating Point pipelines. 43 def P10_BR : ProcResource<2>; // Two Branch pipelines. 44 def P10_CY : ProcResource<4>; // Four Crypto pipelines. 45 def P10_DF : ProcResource<1>; // One Decimal Floating Point pipelines. 48 def P10_FX : ProcResource<4>; // Four ALU pipelines. 49 def P10_LD : ProcResource<2>; // Two Load pipelines. 51 def P10_PM : ProcResource<4>; // Four 128-bit permute (PM) pipelines. 52 def P10_ST : ProcResource<2>; // Two ST-D pipelines. 58 def P10_ANY_SLOT : ProcResource<8>; 63 def P10_EVEN_SLOT : ProcResource<4>; [all …]
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H A D | PPCScheduleP7.td | 37 def P7_LSU_FXU: ProcResource<4>; 38 def P7_LSU: ProcResource<2> { 41 def P7_FXU: ProcResource<2> { 45 def P7_FPU: ProcResource<4>; 54 def P7_VMX: ProcResource<1>; 55 def P7_VPM: ProcResource<1> { 59 def P7_VXS: ProcResource<1> { 62 def P7_DFU: ProcResource<1>; 63 def P7_BRU: ProcResource<1>; 64 def P7_CRU: ProcResource<1>; [all …]
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/freebsd/contrib/llvm-project/llvm/lib/MCA/Stages/ |
H A D | InstructionTables.cpp | 34 const MCProcResourceDesc &ProcResource = *SM.getProcResource(Index); in execute() local 35 unsigned NumUnits = ProcResource.NumUnits; in execute() 36 if (!ProcResource.SubUnitsIdxBegin) { in execute() 50 unsigned SubUnitIdx = ProcResource.SubUnitsIdxBegin[I1]; in execute()
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/freebsd/contrib/llvm-project/llvm/tools/llvm-mca/ |
H A D | PipelinePrinter.cpp | 86 const MCProcResourceDesc &ProcResource = *SM.getProcResource(I); in getJSONTargetInfo() local 87 unsigned NumUnits = ProcResource.NumUnits; in getJSONTargetInfo() 88 if (ProcResource.SubUnitsIdxBegin || !NumUnits) in getJSONTargetInfo() 92 std::string ResourceName = ProcResource.Name; in getJSONTargetInfo()
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/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
H A D | RISCVSchedRocket.td | 29 // Modeling each pipeline as a ProcResource using the BufferSize = 0 since 33 def RocketUnitALU : ProcResource<1>; // Int ALU 34 def RocketUnitIMul : ProcResource<1>; // Int Multiply 35 def RocketUnitMem : ProcResource<1>; // Load/Store 36 def RocketUnitB : ProcResource<1>; // Branch 38 def RocketUnitFPALU : ProcResource<1>; // FP ALU 42 def RocketUnitIDiv : ProcResource<1>; // Int Division 43 def RocketUnitFPDivSqrt : ProcResource<1>; // FP Divide/Sqrt
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H A D | RISCVSchedSiFiveP400.td | 31 def SiFiveP400IEXQ0 : ProcResource<1>; 32 def SiFiveP400IEXQ1 : ProcResource<1>; 33 def SiFiveP400IEXQ2 : ProcResource<1>; 34 def SiFiveP400FEXQ0 : ProcResource<1>; 35 def SiFiveP400Load : ProcResource<1>; 36 def SiFiveP400Store : ProcResource<1>; 43 def SiFiveP400Div : ProcResource<1>; 47 def SiFiveP400FloatDiv : ProcResource<1>;
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H A D | RISCVSchedSyntacoreSCR1.td | 33 def SCR1_ALU : ProcResource<1>; 34 def SCR1_LSU : ProcResource<1>; 35 def SCR1_MUL : ProcResource<1>; 36 def SCR1_DIV : ProcResource<1>; 37 def SCR1_CFU : ProcResource<1>;
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/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
H A D | SISchedule.td | 102 def HWBranch : ProcResource<1> { 105 def HWExport : ProcResource<1> { 108 def HWLGKM : ProcResource<1> { 111 def HWSALU : ProcResource<1> { 114 def HWVMEM : ProcResource<1> { 117 def HWVALU : ProcResource<1> { 120 def HWTransVALU : ProcResource<1> { // Transcendental VALU 123 def HWRC : ProcResource<1> { // Register destination cache 126 def HWXDL : ProcResource<1> { // MFMA CU
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/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
H A D | ARMScheduleM85.td | 39 def M85UnitLoadL : ProcResource<1> { let BufferSize = 0; } 40 def M85UnitLoadH : ProcResource<1> { let BufferSize = 0; } 42 def M85UnitStoreL : ProcResource<1> { let BufferSize = 0; } 43 def M85UnitStoreH : ProcResource<1> { let BufferSize = 0; } 45 def M85UnitALU : ProcResource<2> { let BufferSize = 0; } 46 def M85UnitShift1 : ProcResource<1> { let BufferSize = 0; } 47 def M85UnitShift2 : ProcResource<1> { let BufferSize = 0; } 48 def M85UnitMAC : ProcResource<1> { let BufferSize = 0; } 49 def M85UnitBranch : ProcResource<1> { let BufferSize = 0; } 50 def M85UnitVFPAL : ProcResource<1> { let BufferSize = 0; } [all …]
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H A D | ARMScheduleM7.td | 38 def M7UnitLoadL : ProcResource<1> { let BufferSize = 0; } 39 def M7UnitLoadH : ProcResource<1> { let BufferSize = 0; } 41 def M7UnitStore : ProcResource<1> { let BufferSize = 0; } 42 def M7UnitALU : ProcResource<2>; 43 def M7UnitShift1 : ProcResource<1> { let BufferSize = 0; } 44 def M7UnitShift2 : ProcResource<1> { let BufferSize = 0; } 45 def M7UnitMAC : ProcResource<1> { let BufferSize = 0; } 46 def M7UnitBranch : ProcResource<1> { let BufferSize = 0; } 47 def M7UnitVFP : ProcResource<1> { let BufferSize = 0; } 48 def M7UnitVPortL : ProcResource<1> { let BufferSize = 0; } [all …]
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/freebsd/contrib/llvm-project/llvm/include/llvm/Target/ |
H A D | TargetPfmCounters.td | 21 // Issue counters can be tied to a ProcResource 24 // The name of the ProcResource on which uops are issued. This is used by 27 // ProcResource.
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/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/ |
H A D | MipsScheduleP5600.td | 32 def P5600ALQ : ProcResource<1> { let BufferSize = 16; } 33 def P5600IssueALU : ProcResource<1> { let Super = P5600ALQ; } 47 def P5600AGQ : ProcResource<3> { let BufferSize = 16; } 48 def P5600IssueAL2 : ProcResource<1> { let Super = P5600AGQ; } 49 def P5600IssueCTISTD : ProcResource<1> { let Super = P5600AGQ; } 50 def P5600IssueLDST : ProcResource<1> { let Super = P5600AGQ; } 52 def P5600AL2Div : ProcResource<1>; 54 def P5600CTISTD : ProcResource<1>; 231 def P5600FPQ : ProcResource<3> { let BufferSize = 16; } 236 def P5600FPUDivSqrt : ProcResource<2>; [all …]
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/freebsd/contrib/llvm-project/llvm/lib/Target/Lanai/ |
H A D | LanaiSchedule.td | 54 def ALU : ProcResource<1> { let BufferSize = 0; } 55 def LdSt : ProcResource<1> { let BufferSize = 0; }
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/freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
H A D | X86ScheduleBdVer2.td | 50 def PdEX0 : ProcResource<1>; // ALU, Integer Pipe0 63 def PdFPU0 : ProcResource<1>; // Vector/FPU Pipe0 64 def PdFPU1 : ProcResource<1>; // Vector/FPU Pipe1 65 def PdFPU2 : ProcResource<1>; // Vector/FPU Pipe2 66 def PdFPU3 : ProcResource<1>; // Vector/FPU Pipe3 133 def PdLoad : ProcResource<2> { 141 def PdStore : ProcResource<1> { 166 def PdFPMMA : ProcResource<1>; // PdFPU0 169 def PdFPCVT : ProcResource<1>; // PdFPU0 172 def PdFPXBR : ProcResource<1>; // PdFPU1 [all …]
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