Home
last modified time | relevance | path

Searched refs:RegisterClass (Results 1 – 25 of 98) sorted by relevance

1234

/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DR600RegisterInfo.td174 def R600_LDS_SRC_REG : RegisterClass<"AMDGPU", [i32], 32,
177 def R600_KC0_X : RegisterClass <"AMDGPU", [f32, i32], 32,
180 def R600_KC0_Y : RegisterClass <"AMDGPU", [f32, i32], 32,
183 def R600_KC0_Z : RegisterClass <"AMDGPU", [f32, i32], 32,
186 def R600_KC0_W : RegisterClass <"AMDGPU", [f32, i32], 32,
189 def R600_KC0 : RegisterClass <"AMDGPU", [f32, i32], 32,
193 def R600_KC1_X : RegisterClass <"AMDGPU", [f32, i32], 32,
196 def R600_KC1_Y : RegisterClass <"AMDGPU", [f32, i32], 32,
199 def R600_KC1_Z : RegisterClass <"AMDGPU", [f32, i32], 32,
202 def R600_KC1_W : RegisterClass <"AMDGPU", [f32, i32], 32,
[all …]
H A DMIMGInstructions.td273 list<RegisterClass> addr_types =
398 RegisterClass Addr3RC>
444 RegisterClass DataRC, RegisterClass AddrRC,
469 RegisterClass DataRC, RegisterClass AddrRC,
684 RegisterClass DataRC, RegisterClass AddrRC,
710 RegisterClass DataRC, RegisterClass AddrRC,
897 RegisterClass DataRC, RegisterClass AddrRC,
925 RegisterClass DataRC, RegisterClass AddrRC,
1128 RegisterClass DataRC, RegisterClass AddrRC,
1155 RegisterClass DataRC, RegisterClass AddrRC,
[all …]
H A DSIRegisterInfo.td116 class SIRegisterTuples<list<SubRegIndex> Indices, RegisterClass RC,
141 : RegisterClass <n, rTypes, Align, rList> {
754 def LDS_DIRECT_CLASS : RegisterClass<"AMDGPU", [i32], 32,
1106 : RegisterOperand<!cast<RegisterClass>(RegisterClassName)> {
1113 class RegOrB16 <string RegisterClass, string OperandTypePrefix>
1117 class RegOrF16 <string RegisterClass, string OperandTypePrefix>
1145 class RegOrB32 <string RegisterClass, string OperandTypePrefix>
1149 class RegOrF32 <string RegisterClass, string OperandTypePrefix>
1161 class RegOrF64 <string RegisterClass, string OperandTypePrefix>
1165 class RegOrB64 <string RegisterClass, string OperandTypePrefix>
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsRegisterInfo.td284 RegisterClass<"Mips", regTypes, 32, (add
300 def GPR32ZERO : RegisterClass<"Mips", [i32], 32, (add
320 def GPRMM16 : RegisterClass<"Mips", [i32], 32, (add
326 def GPRMM16Zero : RegisterClass<"Mips", [i32], 32, (add
354 def GPR64 : RegisterClass<"Mips", [i64], 64, (add
368 def CPU16Regs : RegisterClass<"Mips", [i32], 32, (add
401 def AFGR64 : RegisterClass<"Mips", [f64], 64, (add
436 def MSA128B: RegisterClass<"Mips", [v16i8], 128,
438 def MSA128H: RegisterClass<"Mips", [v8i16, v8f16], 128,
440 def MSA128W: RegisterClass<"Mips", [v4i32, v4f32], 128,
[all …]
H A DMipsCondMov.td55 multiclass MovzPats0<RegisterClass CRC, RegisterClass DRC,
80 multiclass MovzPats1<RegisterClass CRC, RegisterClass DRC,
88 multiclass MovzPats2<RegisterClass CRC, RegisterClass DRC,
95 multiclass MovnPats<RegisterClass CRC, RegisterClass DRC, Instruction MOVNInst,
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86RegisterInfo.td545 def GR8 : RegisterClass<"X86", [i8], 8,
557 def GRH8 : RegisterClass<"X86", [i8], 8,
562 def GR16 : RegisterClass<"X86", [i16], 16,
569 def GRH16 : RegisterClass<"X86", [i16], 16,
574 def GR32 : RegisterClass<"X86", [i32], 32,
585 def GR64 : RegisterClass<"X86", [i64], 64,
638 def GR8_NOREX : RegisterClass<"X86", [i8], 8,
646 def GR16_NOREX : RegisterClass<"X86", [i16], 16,
649 def GR32_NOREX : RegisterClass<"X86", [i32], 32,
658 def GR8_NOREX2 : RegisterClass<"X86", [i8], 8,
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/SPIRV/
H A DSPIRVRegisterInfo.td19 def TYPE : RegisterClass<"SPIRV", [i32], 32, (add TYPE0)>;
23 def ID : RegisterClass<"SPIRV", [i32], 32, (add ID0)>;
25 def fID : RegisterClass<"SPIRV", [f32], 32, (add fID0)>;
27 def pID : RegisterClass<"SPIRV", [p0], 32, (add pID0)>;
29 def vID : RegisterClass<"SPIRV", [v2i32], 32, (add vID0)>;
31 def vfID : RegisterClass<"SPIRV", [v2f32], 32, (add vfID0)>;
33 …def ANYID : RegisterClass<"SPIRV", [i32, f32, p0, v2i32, v2f32], 32, (add ID, fID, pID, vID, vfID)…
38 def ANY : RegisterClass<"SPIRV", [i32], 32, (add TYPE, ID)>;
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonPatternsV65.td9 multiclass vgathermh<RegisterClass RC> {
19 multiclass vgathermw<RegisterClass RC> {
29 multiclass vgathermhw<RegisterClass RC> {
43 multiclass vgathermhq<RegisterClass RC1, RegisterClass RC2> {
54 multiclass vgathermwq<RegisterClass RC1, RegisterClass RC2> {
65 multiclass vgathermhwq<RegisterClass RC1, RegisterClass RC2> {
H A DHexagonRegisterInfo.td525 def HvxVQR : RegisterClass<"Hexagon", [untyped], 2048,
542 def IntRegsLow8 : RegisterClass<"Hexagon", [i32], 32,
552 def PredRegs : RegisterClass<"Hexagon",
559 def CtrRegs : RegisterClass<"Hexagon", [i32], 32,
566 def VectRegRev : RegisterClass<"Hexagon", [i64], 64,
573 def CtrRegs64 : RegisterClass<"Hexagon", [i64], 64,
578 def GuestRegs : RegisterClass<"Hexagon", [i32], 32,
588 def GuestRegs64 : RegisterClass<"Hexagon", [i64], 64,
597 def SysRegs : RegisterClass<"Hexagon", [i32], 32,
616 def SysRegs64 : RegisterClass<"Hexagon", [i64], 64,
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMRegisterInfo.td262 def GPRnopc : RegisterClass<"ARM", [i32], 32, (sub GPR, PC)> {
318 def GPRsp : RegisterClass<"ARM", [i32], 32, (add SP)> {
324 def GPRlr : RegisterClass<"ARM", [i32], 32, (add LR)>;
330 def rGPR : RegisterClass<"ARM", [i32], 32, (sub GPR, SP, PC)> {
352 def tGPR : RegisterClass<"ARM", [i32], 32, (trunc GPR, 8)> {
361 def hGPR : RegisterClass<"ARM", [i32], 32, (sub GPR, tGPR)> {
394 def CCR : RegisterClass<"ARM", [i32], 32, (add CPSR)> {
566 def QQPR : RegisterClass<"ARM", [v4i64], 256, (add Tuples2Q)> {
573 def MQQPR : RegisterClass<"ARM", [v4i64], 256, (trunc QQPR, 7)>;
583 def DQuad : RegisterClass<"ARM", [v4i64], 256,
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchFloatInstrFormats.td171 class FP_ALU_2R<bits<32> op, RegisterClass rc = FPR32>
174 class FP_ALU_3R<bits<32> op, RegisterClass rc = FPR32>
177 class FP_ALU_4R<bits<32> op, RegisterClass rc = FPR32>
183 class FP_CMP<bits<32> op, RegisterClass rc = FPR32>
186 class FP_CONV<bits<32> op, RegisterClass rcd = FPR32, RegisterClass rcs = FPR32>
189 class FP_MOV<bits<32> op, RegisterClass rcd = FPR32, RegisterClass rcs = FPR32>
192 class FP_SEL<bits<32> op, RegisterClass rc = FPR32>
205 class FP_LOAD_3R<bits<32> op, RegisterClass rc = FPR32>
208 class FP_LOAD_2RI12<bits<32> op, RegisterClass rc = FPR32>
214 class FP_STORE_3R<bits<32> op, RegisterClass rc = FPR32>
[all …]
H A DLoongArchRegisterInfo.td102 def GPR : RegisterClass<"LoongArch", [GRLenVT], 32, (add
120 def GPRT : RegisterClass<"LoongArch", [GRLenVT], 32, (add
170 def FPR32 : RegisterClass<"LoongArch", [f32], 32, (sequence "F%u", 0, 31)>;
171 def FPR64 : RegisterClass<"LoongArch", [f64], 64, (sequence "F%u_64", 0, 31)>;
178 def CFR : RegisterClass<"LoongArch", [GRLenVT], 32, (sequence "FCC%u", 0, 7)> {
188 def FCSR : RegisterClass<"LoongArch", [i32], 32, (sequence "FCSR%u", 0, 3)>;
196 def LSX128 : RegisterClass<"LoongArch",
206 def LASX256 : RegisterClass<"LoongArch",
216 def SCR : RegisterClass<"LoongArch", [GRLenVT], 32, (sequence "SCR%u", 0, 3)>;
/freebsd/contrib/llvm-project/llvm/lib/Target/AVR/
H A DAVRRegisterInfo.td114 def GPR8 : RegisterClass<"AVR", [i8], 8,
125 def GPR8lo : RegisterClass<"AVR", [i8], 8,
130 def LD8 : RegisterClass<"AVR", [i8], 8,
140 def LD8lo : RegisterClass<"AVR", [i8], 8,
144 def DREGS : RegisterClass<"AVR", [i16], 8,
159 : RegisterClass<"AVR", [i16], 8,
163 def DREGSLD8lo : RegisterClass<"AVR", [i16], 8,
171 def DREGSMOVW : RegisterClass<"AVR", [i16], 8,
182 def DLDREGS : RegisterClass<"AVR", [i16], 8,
192 def IWREGS : RegisterClass<"AVR", [i16], 8,
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/
H A DCSKYRegisterInfo.td152 def GPR : RegisterClass<"CSKY", [i32], 32,
162 def sGPR : RegisterClass<"CSKY", [i32], 32,
170 def mGPR : RegisterClass<"CSKY", [i32], 32,
176 def GPRSP : RegisterClass<"CSKY", [i32], 32, (add R14)> {
184 def CARRY : RegisterClass<"CSKY", [i32], 32, (add C)> {
191 def FPR32 : RegisterClass<"CSKY", [f32], 32,
193 def sFPR32 : RegisterClass<"CSKY", [f32], 32,
196 def FPR64 : RegisterClass<"CSKY", [f64], 32,
198 def sFPR64 : RegisterClass<"CSKY", [f64], 32,
203 def FPR128 : RegisterClass<"CSKY",
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64RegisterInfo.td156 def GPR64common : RegisterClass<"AArch64", [i64], 64,
252 def CCR : RegisterClass<"AArch64", [i32], 32, (add NZCV)> {
450 def FPR64_lo : RegisterClass<"AArch64",
458 def FPR128 : RegisterClass<"AArch64",
465 def FPR128_lo : RegisterClass<"AArch64",
472 def FPR128_0to7 : RegisterClass<"AArch64",
566 multiclass VectorList<int count, RegisterClass Reg64, RegisterClass Reg128> {
873 RegisterClass RC> : RegisterOperand<RC> {
889 class PPRClass<int firstreg, int lastreg> : RegisterClass<
926 class PNRClass<int firstreg, int lastreg> : RegisterClass<
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/VE/
H A DVEInstrVec.td469 multiclass VBRDm<string opcStr, bits<8>opc, RegisterClass VRC, RegisterClass RC,
514 RegisterClass RCM> {
556 multiclass RVm<string opcStr, bits<8>opc, RegisterClass VRC, RegisterClass RC,
569 RegisterClass RC, RegisterClass RCM, Operand SIMM = simm7> {
585 RegisterClass RC, RegisterClass RCM> {
597 RegisterClass RCM> {
605 RegisterClass RCM> {
613 RegisterClass RC, RegisterClass RCM> {
662 multiclass RVMm<string opcStr, bits<8>opc, RegisterClass VRC, RegisterClass RC,
713 RegisterClass RC> {
[all …]
H A DVERegisterInfo.td77 def MISC : RegisterClass<"VE", [i64], 64,
95 def VLS : RegisterClass<"VE", [i32], 64, (add VL)>;
173 def I32 : RegisterClass<"VE", [i32], 32,
177 def I64 : RegisterClass<"VE", [i64, f64], 64,
181 def F32 : RegisterClass<"VE", [f32], 32,
185 def F128 : RegisterClass<"VE", [f128], 128,
190 def V64 : RegisterClass<"VE",
198 def VM : RegisterClass<"VE", [v256i1], 64, (sequence "VM%u", 0, 15)>;
199 def VM512 : RegisterClass<"VE", [v512i1], 64, (sequence "VMP%u", 0, 7)>;
/freebsd/contrib/llvm-project/llvm/lib/Target/Sparc/
H A DSparcRegisterInfo.td342 def IntRegs : RegisterClass<"SP", [i32, i64], 32,
349 def IntPair : RegisterClass<"SP", [v2i32], 64,
359 def I64Regs : RegisterClass<"SP", [i64], 64, (add IntRegs)>;
362 def FPRegs : RegisterClass<"SP", [f32], 32, (sequence "F%u", 0, 31)>;
363 def DFPRegs : RegisterClass<"SP", [f64], 64, (sequence "D%u", 0, 31)>;
364 def QFPRegs : RegisterClass<"SP", [f128], 128, (sequence "Q%u", 0, 15)>;
371 def FCCRegs : RegisterClass<"SP", [i1], 1, (sequence "FCC%u", 0, 3)>;
382 def ASRRegs : RegisterClass<"SP", [i32], 32,
386 def CoprocRegs : RegisterClass<"SP", [i32], 32,
390 def CoprocPair : RegisterClass<"SP", [v2i32], 64,
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCRegisterInfoDMR.td136 def DMRROWRC : RegisterClass<"PPC", [v128i1], 128,
141 def DMRROWpRC : RegisterClass<"PPC", [v256i1], 128,
146 def WACCRC : RegisterClass<"PPC", [v512i1], 128,
151 def WACC_HIRC : RegisterClass<"PPC", [v512i1], 128,
156 def DMRRC : RegisterClass<"PPC", [v1024i1], 128,
161 def DMRpRC : RegisterClass<"PPC", [v2048i1], 128,
H A DPPCRegisterInfo.td382 def F4RC : RegisterClass<"PPC", [f32], 32, (add F8RC)>;
392 RegisterClass<"PPC", [ppcf128], 128,
399 def VRRC : RegisterClass<"PPC",
415 def VFRC : RegisterClass<"PPC", [f64], 64,
429 def VSSRC : RegisterClass<"PPC", [f32], 32, (add VSFRC)>;
431 def CRBITRC : RegisterClass<"PPC", [i1], 32,
449 def CRRC : RegisterClass<"PPC", [i32], 32,
461 def CTRRC : RegisterClass<"PPC", [i32], 32, (add CTR)> {
468 def LRRC : RegisterClass<"PPC", [i32], 32, (add LR)> {
471 def LR8RC : RegisterClass<"PPC", [i64], 64, (add LR8)> {
[all …]
/freebsd/contrib/llvm-project/llvm/include/llvm/Target/GlobalISel/
H A DRegisterBank.td12 class RegisterBank<string name, list<RegisterClass> classes> {
14 list<RegisterClass> RegisterClasses = classes;
/freebsd/contrib/llvm-project/llvm/lib/Target/ARC/
H A DARCRegisterInfo.td63 def GPR32: RegisterClass<"ARC", [i32], 32,
75 def SREG : RegisterClass<"ARC", [i32], 1, (add STATUS32)>;
77 def GPR_S : RegisterClass<"ARC", [i32], 8,
/freebsd/contrib/llvm-project/llvm/lib/Target/BPF/
H A DBPFRegisterInfo.td39 def GPR32 : RegisterClass<"BPF", [i32], 64, (add
46 def GPR : RegisterClass<"BPF", [i64], 64, (add
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVRegisterInfo.td227 def FPR16 : RegisterClass<"RISCV", [f16, bf16], 16, (add
236 def FPR32 : RegisterClass<"RISCV", [f32], 32, (add
245 def FPR32C : RegisterClass<"RISCV", [f32], 32, (add
252 def FPR64 : RegisterClass<"RISCV", [f64], 64, (add
261 def FPR64C : RegisterClass<"RISCV", [f64], 64, (add
462 def VCSR : RegisterClass<"RISCV", [XLenVT], 32,
481 : RegisterClass<"RISCV",
535 def VMV0 : RegisterClass<"RISCV", VMaskVTs, 64, (add V0)> {
540 def GPRF16 : RegisterClass<"RISCV", [f16], 16, (add GPR)>;
541 def GPRF32 : RegisterClass<"RISCV", [f32], 32, (add GPR)>;
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/XCore/
H A DXCoreRegisterInfo.td44 def GRRegs : RegisterClass<"XCore", [i32], 32,
53 def RRegs : RegisterClass<"XCore", [i32], 32,

1234