/freebsd/contrib/llvm-project/llvm/include/llvm/MC/ |
H A D | MCSymbolXCOFF.h | 54 void setVisibilityType(XCOFF::VisibilityType SVT) { VisibilityType = SVT; }; in setVisibilityType() argument
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/freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
H A D | TargetLoweringBase.cpp | 1009 MVT SVT = VT.getSimpleVT(); in getTypeConversion() local 1011 MVT NVT = TransformToType[SVT.SimpleTy]; in getTypeConversion() 1477 MVT SVT = (MVT::SimpleValueType) nVT; in computeRegisterProperties() local 1481 SVT.getVectorElementCount() == EC && isTypeLegal(SVT)) { in computeRegisterProperties() 1482 TransformToType[i] = SVT; in computeRegisterProperties() 1483 RegisterTypeForVT[i] = SVT; in computeRegisterProperties() 1499 MVT SVT = (MVT::SimpleValueType) nVT; in computeRegisterProperties() local 1500 if (SVT.getVectorElementType() == EltVT && in computeRegisterProperties() 1504 isTypeLegal(SVT)) { in computeRegisterProperties() 1505 TransformToType[i] = SVT; in computeRegisterProperties() [all …]
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/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
H A D | LegalizeFloatTypes.cpp | 868 if (NVT.bitsGE(SVT)) in SoftenFloatRes_XINT_TO_FP() 879 CallOptions.setTypeListBeforeSoften(SVT, RVT, true); in SoftenFloatRes_XINT_TO_FP() 977 EVT SVT = Op.getValueType(); in SoftenFloatOp_FP_ROUND() local 1052 EVT SVT = Op.getValueType(); in SoftenFloatOp_FP_TO_XINT() local 2999 EVT SVT = N->getOperand(0).getValueType(); in SoftPromoteHalfRes_FP_ROUND() local 3191 EVT SVT = Op.getValueType(); in SoftPromoteHalfOp_FP_EXTEND() local 3195 assert(SVT == MVT::f16); in SoftPromoteHalfOp_FP_EXTEND() 3210 EVT SVT = Op.getValueType(); in SoftPromoteHalfOp_FP_TO_XINT() local 3225 EVT SVT = Op.getValueType(); in SoftPromoteHalfOp_FP_TO_XINT_SAT() local 3245 EVT SVT = Op0.getValueType(); in SoftPromoteHalfOp_SELECT_CC() local [all …]
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H A D | SelectionDAG.cpp | 2958 EVT LegalSVT = SVT; in getSplatValue() 2960 if (!SVT.isInteger()) in getSplatValue() 2963 if (LegalSVT.bitsLT(SVT)) in getSplatValue() 5523 EVT SVT = VT.getScalarType(); in foldCONCAT_VECTORS() local 5538 SVT = (SVT.bitsLT(Op.getValueType()) ? Op.getValueType() : SVT); in foldCONCAT_VECTORS() 5543 Op = DAG.getUNDEF(SVT); in foldCONCAT_VECTORS() 6412 if (LegalSVT != SVT) in FoldConstantArithmetic() 8680 if (VT == SVT) in getTruncStore() 8698 ID.AddInteger(SVT.getRawBits()); in getTruncStore() 8930 if (VT == SVT) in getTruncStoreVP() [all …]
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H A D | LegalizeDAG.cpp | 315 EVT SVT = VT; in ExpandConstantFP() local 320 while (SVT != MVT::f32 && SVT != MVT::f16 && SVT != MVT::bf16) { in ExpandConstantFP() 321 SVT = (MVT::SimpleValueType)(SVT.getSimpleVT().SimpleTy - 1); in ExpandConstantFP() 330 VT = SVT; in ExpandConstantFP() 916 EVT SVT = SrcVT.getScalarType(); in LegalizeLoadOps() local 917 if (SVT == MVT::f16 || SVT == MVT::bf16) { in LegalizeLoadOps() 3648 MVT SVT = Op.getSimpleValueType(); in ExpandNode() local 3649 if ((SVT == MVT::f64 || SVT == MVT::f80) && in ExpandNode() 4682 if (NVT.bitsGE(SVT)) in ConvertNodeToLibcall() 4711 EVT SVT = Op.getValueType(); in ConvertNodeToLibcall() local [all …]
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H A D | LegalizeIntegerTypes.cpp | 365 EVT SVT = getSetCCResultType(N->getOperand(2).getValueType()); in PromoteIntRes_AtomicCmpSwap() local 370 if (!TLI.isTypeLegal(SVT)) in PromoteIntRes_AtomicCmpSwap() 371 SVT = NVT; in PromoteIntRes_AtomicCmpSwap() 713 EVT SVT = In.getValueType().getScalarType(); in PromoteIntRes_EXTRACT_VECTOR_ELT() local 714 if (SVT.bitsGE(NVT)) { in PromoteIntRes_EXTRACT_VECTOR_ELT() 918 EVT SVT = getSetCCResultType(VT); in PromoteIntRes_Overflow() local 1233 EVT SVT = getSetCCResultType(InVT); in PromoteIntRes_SETCC() local 1238 if (getTypeAction(SVT) == TargetLowering::TypePromoteInteger) { in PromoteIntRes_SETCC() 1241 SVT = getSetCCResultType(InVT); in PromoteIntRes_SETCC() 1244 SVT = NVT; in PromoteIntRes_SETCC() [all …]
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H A D | DAGCombiner.cpp | 12768 EVT SVT = VT.getScalarType(); in tryToFoldExtendOfConstant() local 13270 if (SVT != N0.getValueType()) { in foldSextSetcc() 14796 EVT SVT = VT.getScalarType(); in visitTRUNCATE() local 14810 EVT SVT = VT.getScalarType(); in visitTRUNCATE() local 23897 EVT SVT = VT.getScalarType(); in visitCONCAT_VECTORS() local 23899 EVT MinVT = SVT; in visitCONCAT_VECTORS() 23900 if (!SVT.isFloatingPoint()) { in visitCONCAT_VECTORS() 24792 EVT SVT = VT.getScalarType(); in combineShuffleOfScalars() local 24793 if (SVT.isInteger()) in combineShuffleOfScalars() 24795 SVT = (SVT.bitsLT(Op.getValueType()) ? Op.getValueType() : SVT); in combineShuffleOfScalars() [all …]
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H A D | TargetLowering.cpp | 6026 EVT SVT = VT.getScalarType(); in BuildExactSDIV() local 6159 EVT SVT = VT.getScalarType(); in BuildSDIV() local 6321 EVT SVT = VT.getScalarType(); in BuildUDIV() local 6392 dl, SVT); in BuildUDIV() 6574 EVT SVT = VT.getScalarType(); in prepareUREMEqFold() local 6664 PAmts.push_back(DAG.getConstant(P, DL, SVT)); in prepareUREMEqFold() 6667 QAmts.push_back(DAG.getConstant(Q, DL, SVT)); in prepareUREMEqFold() 6823 EVT SVT = VT.getScalarType(); in prepareSREMEqFold() local 6917 PAmts.push_back(DAG.getConstant(P, DL, SVT)); in prepareSREMEqFold() 6918 AAmts.push_back(DAG.getConstant(A, DL, SVT)); in prepareSREMEqFold() [all …]
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H A D | LegalizeVectorTypes.cpp | 6729 EVT SVT = getSetCCResultType(InOp0.getValueType()); in WidenVecOp_SETCC() local 6732 SVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1, in WidenVecOp_SETCC() 6733 SVT.getVectorElementCount()); in WidenVecOp_SETCC() 6736 SVT, InOp0, InOp1, N->getOperand(2)); in WidenVecOp_SETCC() 6740 SVT.getVectorElementType(), in WidenVecOp_SETCC()
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/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
H A D | ValueTypes.h | 41 constexpr EVT(MVT::SimpleValueType SVT) : V(SVT) {} in EVT()
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H A D | MachineValueType.h | 61 constexpr MVT(SimpleValueType SVT) : SimpleTy(SVT) {} in MVT() argument
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H A D | SelectionDAG.h | 1402 MachinePointerInfo PtrInfo, EVT SVT, Align Alignment, 1407 MachinePointerInfo PtrInfo, EVT SVT, 1411 return getTruncStore(Chain, dl, Val, Ptr, PtrInfo, SVT, 1412 Alignment.value_or(getEVTAlign(SVT)), MMOFlags, 1416 SDValue Ptr, EVT SVT, MachineMemOperand *MMO); 1468 MachinePointerInfo PtrInfo, EVT SVT, Align Alignment, 1472 SDValue Ptr, SDValue Mask, SDValue EVL, EVT SVT, 1536 EVT SVT, Align Alignment, 1542 SDValue EVL, EVT SVT, MachineMemOperand *MMO,
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/freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
H A D | X86InstCombineIntrinsic.cpp | 204 Type *SVT = VT->getElementType(); in simplifyX86immShift() local 207 unsigned BitWidth = SVT->getPrimitiveSizeInBits(); in simplifyX86immShift() 217 Amt = Builder.CreateZExtOrTrunc(Amt, SVT); in simplifyX86immShift() 226 Amt = ConstantInt::get(SVT, BitWidth - 1); in simplifyX86immShift() 233 cast<VectorType>(AmtVT)->getElementType() == SVT && in simplifyX86immShift() 260 cast<VectorType>(AmtVT)->getElementType() == SVT && in simplifyX86immShift() 352 Type *SVT = VT->getElementType(); in simplifyX86varShift() local 354 int BitWidth = SVT->getIntegerBitWidth(); in simplifyX86varShift() 406 ConstantVec.push_back(UndefValue::get(SVT)); in simplifyX86varShift() 423 ShiftVecAmts.push_back(UndefValue::get(SVT)); in simplifyX86varShift() [all …]
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H A D | X86ISelLowering.cpp | 4157 DstVT = MVT::getVectorVT(SVT, 512 / SVT.getSizeInBits()); in getAVX512Node() 21328 if (!SVT.isVector()) in LowerFP_EXTEND() 21383 if (SVT == MVT::f128 || (VT == MVT::f16 && SVT == MVT::f80)) in LowerFP_ROUND() 21386 if (VT == MVT::f16 && (SVT == MVT::f64 || SVT == MVT::f32) && in LowerFP_ROUND() 24225 if (SVT != MVT::i64 && SVT != MVT::i32 && SVT != MVT::i16) in LowerEXTEND_VECTOR_INREG() 44344 if (SVT != MVT::i64 && SVT != MVT::i32 && SVT != MVT::i16 && SVT != MVT::i8) in combineToExtendBoolVectorInReg() 49738 (SVT == MVT::i8 || SVT == MVT::i16) && in combineTruncateWithSat() 49763 (SVT == MVT::i32 || SVT == MVT::i16 || SVT == MVT::i8)) { in combineTruncateWithSat() 51643 !(SVT == MVT::f32 || SVT == MVT::f64) || in getNegatedExpression() 52593 if (SVT != MVT::i8 && SVT != MVT::i16 && SVT != MVT::i32 && in combineExtSetcc() [all …]
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/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
H A D | HexagonISelDAGToDAG.cpp | 1247 EVT SVT = (UW == 32 || UW == 64) ? MVT::getIntegerVT(UW) : UVT; in ppHoistZextI1() local 1248 SDValue Sel = DAG.getNode(ISD::SELECT, dl, SVT, OpI1, in ppHoistZextI1() 1249 DAG.getBitcast(SVT, If1), in ppHoistZextI1() 1250 DAG.getBitcast(SVT, If0)); in ppHoistZextI1()
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H A D | HexagonISelLowering.cpp | 3778 MVT SVT = VT.getSimpleVT(); in allowsMemoryAccess() local 3779 if (Subtarget.isHVXVectorType(SVT, true)) in allowsMemoryAccess() 3780 return allowsHvxMemoryAccess(SVT, Flags, Fast); in allowsMemoryAccess() 3788 MVT SVT = VT.getSimpleVT(); in allowsMisalignedMemoryAccesses() local 3789 if (Subtarget.isHVXVectorType(SVT, true)) in allowsMisalignedMemoryAccesses() 3790 return allowsHvxMisalignedMemoryAccesses(SVT, Flags, Fast); in allowsMisalignedMemoryAccesses()
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H A D | HexagonISelDAGToDAGHVX.cpp | 1178 MVT::SimpleValueType SVT = MVT::SimpleValueType(R.OpN & OpRef::Index); in materialize() local 1179 Ops.push_back(ISel.selectUndef(dl, MVT(SVT))); in materialize()
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/freebsd/contrib/llvm-project/llvm/utils/TableGen/ |
H A D | GlobalISelMatchTable.cpp | 429 std::optional<LLTCodeGen> MVTToLLT(MVT::SimpleValueType SVT) { in MVTToLLT() argument 430 MVT VT(SVT); in MVTToLLT()
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H A D | GlobalISelMatchTable.h | 283 std::optional<LLTCodeGen> MVTToLLT(MVT::SimpleValueType SVT);
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/freebsd/contrib/file/magic/Magdir/ |
H A D | sysex | 211 >>>4 byte 0x04 SVT (Velocity Curve)
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/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
H A D | RISCVISelLowering.cpp | 4770 MVT SVT = VT.getVectorElementType(); in lowerVECTOR_SHUFFLE() local 4788 Offset *= SVT.getStoreSize(); in lowerVECTOR_SHUFFLE() 4793 if (SVT.isInteger() && SVT.bitsGT(XLenVT)) { in lowerVECTOR_SHUFFLE() 4804 ISD::INTRINSIC_W_CHAIN, DL, VTs, Ops, SVT, in lowerVECTOR_SHUFFLE() 4814 if (SVT.isFloatingPoint()) in lowerVECTOR_SHUFFLE() 4815 V = DAG.getLoad(SVT, DL, Ld->getChain(), NewAddr, in lowerVECTOR_SHUFFLE() 5101 MVT SVT = VT.getSimpleVT(); in isShuffleMaskLegal() local 5104 if (SVT.getScalarType() == MVT::i1) in isShuffleMaskLegal() 19655 EVT SVT = VT.getScalarType(); in isFMAFasterThanFMulAndFAdd() local 19657 if (!SVT.isSimple()) in isFMAFasterThanFMulAndFAdd() [all …]
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/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
H A D | PPCISelLowering.cpp | 6956 static const TargetRegisterClass *getRegClassForSVT(MVT::SimpleValueType SVT, in getRegClassForSVT() argument 6960 assert((IsPPC64 || SVT != MVT::i64) && in getRegClassForSVT() 6963 switch (SVT) { in getRegClassForSVT() 7147 MVT::SimpleValueType SVT = VA.getLocVT().SimpleTy; in LowerFormalArguments_AIX() local 7149 getRegClassForSVT(SVT, IsPPC64, Subtarget.hasP8Vector(), in LowerFormalArguments_AIX() 7288 MVT::SimpleValueType SVT = ValVT.SimpleTy; in LowerFormalArguments_AIX() local 7291 getRegClassForSVT(SVT, IsPPC64, Subtarget.hasP8Vector(), in LowerFormalArguments_AIX() 11722 EVT SVT = getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), in ReplaceNodeResults() local 11724 SDVTList VTs = DAG.getVTList(SVT, MVT::Other); in ReplaceNodeResults()
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/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/ |
H A D | MipsSEISelLowering.cpp | 418 MVT::SimpleValueType SVT = VT.getSimpleVT().SimpleTy; in allowsMisalignedMemoryAccesses() local 430 switch (SVT) { in allowsMisalignedMemoryAccesses()
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/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
H A D | SIISelLowering.cpp | 14614 MVT SVT = Node->getValueType(0).getVectorElementType().getSimpleVT(); in adjustWritemask() local 14617 SVT : MVT::getVectorVT(SVT, NewChannels == 3 ? 4 : in adjustWritemask()
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/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
H A D | ARMISelLowering.cpp | 8785 EVT SVT = VT.getScalarType() == MVT::i8 || VT.getScalarType() == MVT::i16 in LowerVECTOR_SHUFFLEUsingOneOff() local 8789 ISD::EXTRACT_VECTOR_ELT, dl, SVT, in LowerVECTOR_SHUFFLEUsingOneOff() 20655 const SDNode *N, MVT::SimpleValueType SVT) { in getDivRemLibcall() argument 20662 switch (SVT) { in getDivRemLibcall()
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