/freebsd/sys/contrib/dev/mediatek/mt76/mt76x2/ |
H A D | usb_mac.c | 104 rts_cfg = mt76_rr(dev, MT_TX_RTS_CFG); in mt76x2u_mac_stop() 112 val = mt76_rr(dev, MT_VEND_ADDR(CFG, MT_USB_U3DMA_CFG)); in mt76x2u_mac_stop() 120 if (!(mt76_rr(dev, 0x0438) & 0xffffffff) && in mt76x2u_mac_stop() 121 !(mt76_rr(dev, 0x0a30) & 0x000000ff) && in mt76x2u_mac_stop() 122 !(mt76_rr(dev, 0x0a34) & 0xff00ff00)) in mt76x2u_mac_stop() 134 if (!(mt76_rr(dev, MT_MAC_STATUS) & MT_MAC_STATUS_TX) && in mt76x2u_mac_stop() 135 !mt76_rr(dev, MT_BBP(IBI, 12))) { in mt76x2u_mac_stop() 152 if (!(mt76_rr(dev, 0x0430) & 0x00ff0000) && in mt76x2u_mac_stop() 153 !(mt76_rr(dev, 0x0a30) & 0xffffffff) && in mt76x2u_mac_stop() 154 !(mt76_rr(dev, 0x0a34) & 0xffffffff) && in mt76x2u_mac_stop() [all …]
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H A D | mac.c | 20 rts_cfg = mt76_rr(dev, MT_TX_RTS_CFG); in mt76x2_mac_stop() 25 if ((mt76_rr(dev, MT_MAC_STATUS) & in mt76x2_mac_stop() 27 mt76_rr(dev, MT_BBP(IBI, 12))) { in mt76x2_mac_stop()
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H A D | phy.c | 18 mt76_rr(dev, MT_BBP(AGC, reg))); in mt76x2_adjust_high_lna_gain() 28 gain = FIELD_GET(MT_BBP_AGC_GAIN, mt76_rr(dev, MT_BBP(AGC, reg))); in mt76x2_adjust_agc_gain() 218 if (mt76_rr(dev, MT_BBP(CORE, 34)) & BIT(4)) in mt76x2_phy_tssi_compensate() 302 val = mt76_rr(dev, MT_BBP(AGC, 26)) & ~0xf; in mt76x2_phy_update_channel_gain() 347 mt76_rr(dev, MT_RX_STAT_1); in mt76x2_phy_update_channel_gain()
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H A D | usb_init.c | 15 u32 val = mt76_rr(dev, MT_VEND_ADDR(CFG, MT_USB_U3DMA_CFG)); in mt76x2u_init_dma() 118 val = mt76_rr(dev, MT_VEND_ADDR(EEPROM, i)); in mt76x2u_init_eeprom() 160 dev->mt76.rxfilter = mt76_rr(dev, MT_RX_FILTR_CFG); in mt76x2u_init_hardware()
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/freebsd/sys/contrib/dev/mediatek/mt76/mt7915/ |
H A D | coredump.c | 173 dump->last_msg_id = mt76_rr(dev, MT_FW_LAST_MSG_ID); in mt7915_coredump_fw_trace() 180 irq = mt76_rr(dev, base + 0x8); in mt7915_coredump_fw_trace() 185 sch = mt76_rr(dev, MT_FW_SCHED_INFO); in mt7915_coredump_fw_trace() 252 dump->taskq[0].read = mt76_rr(dev, MT_FW_TASK_QID1); in mt7915_coredump_fw_task() 254 dump->taskq[1].read = mt76_rr(dev, MT_FW_TASK_QID2); in mt7915_coredump_fw_task() 260 dump->taski[0].start = mt76_rr(dev, MT_FW_TASK_START); in mt7915_coredump_fw_task() 261 dump->taski[0].end = mt76_rr(dev, MT_FW_TASK_END); in mt7915_coredump_fw_task() 262 dump->taski[0].size = mt76_rr(dev, MT_FW_TASK_SIZE); in mt7915_coredump_fw_task() 273 count = mt76_rr(dev, MT_FW_CIRQ_COUNT); in mt7915_coredump_fw_context() 286 idx = mt76_rr(dev, MT_FW_TASK_IDX); in mt7915_coredump_fw_context() [all …]
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H A D | mac.c | 192 val = mt76_rr(dev, addr); in mt7915_mac_sta_poll() 223 val = mt76_rr(dev, addr); in mt7915_mac_sta_poll() 1270 val = mt76_rr(dev, reg); in mt7915_phy_get_nf() 1739 cnt = mt76_rr(dev, MT_MIB_SDR3(band)); in mt7915_mac_update_stats() 1744 cnt = mt76_rr(dev, MT_MIB_SDR4(band)); in mt7915_mac_update_stats() 1747 cnt = mt76_rr(dev, MT_MIB_SDR5(band)); in mt7915_mac_update_stats() 1750 cnt = mt76_rr(dev, MT_MIB_SDR6(band)); in mt7915_mac_update_stats() 1753 cnt = mt76_rr(dev, MT_MIB_SDR7(band)); in mt7915_mac_update_stats() 1757 cnt = mt76_rr(dev, MT_MIB_SDR8(band)); in mt7915_mac_update_stats() 1848 cnt = mt76_rr(dev, MT_MIB_DR8(band)); in mt7915_mac_update_stats() [all …]
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H A D | debugfs.c | 166 mt76_rr(dev, MT_SWDEF_SER_STATS)); in mt7915_sys_recovery_get() 169 mt76_rr(dev, MT_SWDEF_PLE_STATS)); in mt7915_sys_recovery_get() 172 mt76_rr(dev, MT_SWDEF_PLE1_STATS)); in mt7915_sys_recovery_get() 175 mt76_rr(dev, MT_SWDEF_PLE_AMSDU_STATS)); in mt7915_sys_recovery_get() 178 mt76_rr(dev, MT_SWDEF_PSE_STATS)); in mt7915_sys_recovery_get() 181 mt76_rr(dev, MT_SWDEF_PSE1_STATS)); in mt7915_sys_recovery_get() 652 mt76_rr(dev, MT_CPU_UTIL_BUSY_PCT), in mt7915_fw_util_wm_show() 655 mt76_rr(dev, MT_CPU_UTIL_IDLE_CNT), in mt7915_fw_util_wm_show() 799 val = mt76_rr(dev, MT_FL_Q_EMPTY); in mt7915_hw_queue_read() 889 val = mt76_rr(dev, MT_PLE_FREEPG_CNT); in mt7915_hw_queues_show() [all …]
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H A D | soc.c | 48 ret = read_poll_timeout(mt76_rr, cur, !(cur & MT_TOP_SPI_POLLING_BIT), in mt76_wmac_spi_read() 64 *val = mt76_rr(dev, MT_TOP_SPI_READ_DATA_CR(adie)); in mt76_wmac_spi_read() 153 read_poll_timeout(mt76_rr, cur, in mt76_wmac_spi_lock() 325 mt76_rr(dev, MT_CONN_INFRA_EFUSE); in mt798x_wmac_coninfra_setup() 906 read_poll_timeout(mt76_rr, cur, !(cur & MT_SLP_CTRL_BSY_MASK), in mt7986_wmac_clock_enable() 914 read_poll_timeout(mt76_rr, cur, !(cur & MT_SLP_CTRL_BSY_MASK), in mt7986_wmac_clock_enable() 950 return read_poll_timeout(mt76_rr, cur, (cur == 0x1d1e), in mt7986_wmac_wm_enable() 963 return read_poll_timeout(mt76_rr, cur, in mt7986_wmac_wfsys_poweron() 984 ret = read_poll_timeout(mt76_rr, cur, in mt7986_wmac_wfsys_setting() 997 return read_poll_timeout(mt76_rr, cur, (cur == 0x02060000), in mt7986_wmac_wfsys_setting() [all …]
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/freebsd/sys/contrib/dev/mediatek/mt76/ |
H A D | mt792x_mac.c | 102 val = mt76_rr(dev, MT_MIB_SDR32(0)); in mt792x_mac_update_mib_stats() 106 val = mt76_rr(dev, MT_ETBF_TX_APP_CNT(0)); in mt792x_mac_update_mib_stats() 110 val = mt76_rr(dev, MT_ETBF_RX_FB_CNT(0)); in mt792x_mac_update_mib_stats() 119 mib->rx_ba_cnt += mt76_rr(dev, MT_MIB_SDR31(0)); in mt792x_mac_update_mib_stats() 130 val = mt76_rr(dev, MT_TX_AGG_CNT(0, i)); in mt792x_mac_update_mib_stats() 131 val2 = mt76_rr(dev, MT_TX_AGG_CNT2(0, i)); in mt792x_mac_update_mib_stats() 202 mt76_rr(dev, MT_TX_AGG_CNT(0, i)); in mt792x_mac_reset_counters() 203 mt76_rr(dev, MT_TX_AGG_CNT2(0, i)); in mt792x_mac_reset_counters() 210 mt76_rr(dev, MT_MIB_SDR9(0)); in mt792x_mac_reset_counters() 211 mt76_rr(dev, MT_MIB_SDR36(0)); in mt792x_mac_reset_counters() [all …]
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H A D | mt76x02_mac.c | 15 mt76_rr(dev, MT_RX_STAT_0); in mt76x02_mac_reset_counters() 16 mt76_rr(dev, MT_RX_STAT_1); in mt76x02_mac_reset_counters() 17 mt76_rr(dev, MT_RX_STAT_2); in mt76x02_mac_reset_counters() 18 mt76_rr(dev, MT_TX_STA_0); in mt76x02_mac_reset_counters() 19 mt76_rr(dev, MT_TX_STA_1); in mt76x02_mac_reset_counters() 20 mt76_rr(dev, MT_TX_STA_2); in mt76x02_mac_reset_counters() 23 mt76_rr(dev, MT_TX_AGG_CNT(i)); in mt76x02_mac_reset_counters() 26 mt76_rr(dev, MT_TX_STAT_FIFO); in mt76x02_mac_reset_counters() 1133 mt76_rr(dev, MT_ED_CCA_TIMER); in mt76x02_edcca_init() 1229 mt76_rr(dev, MT_CH_BUSY); in mt76x02_mac_cc_reset() [all …]
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H A D | mt76x02_dfs.c | 232 current_ts = mt76_rr(dev, MT_PBF_LIFE_TIMER); in mt76x02_dfs_check_chirp() 257 pulse->period = mt76_rr(dev, MT_BBP(DFS, 19)); in mt76x02_dfs_get_hw_pulse() 260 pulse->w1 = mt76_rr(dev, MT_BBP(DFS, 20)); in mt76x02_dfs_get_hw_pulse() 261 pulse->w2 = mt76_rr(dev, MT_BBP(DFS, 23)); in mt76x02_dfs_get_hw_pulse() 264 pulse->burst = mt76_rr(dev, MT_BBP(DFS, 22)); in mt76x02_dfs_get_hw_pulse() 376 data = mt76_rr(dev, MT_BBP(DFS, 37)); in mt76x02_dfs_fetch_event() 381 data = mt76_rr(dev, MT_BBP(DFS, 37)); in mt76x02_dfs_fetch_event() 383 data = mt76_rr(dev, MT_BBP(DFS, 37)); in mt76x02_dfs_fetch_event() 641 engine_mask = mt76_rr(dev, MT_BBP(DFS, 1)); in mt76x02_dfs_tasklet() 799 agc_r8 = mt76_rr(dev, MT_BBP(AGC, 8)); in mt76x02_phy_dfs_adjust_agc() [all …]
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H A D | mt76x02_eeprom.c | 18 val = mt76_rr(dev, MT_EFUSE_CTRL); in mt76x02_efuse_read() 31 val = mt76_rr(dev, MT_EFUSE_CTRL); in mt76x02_efuse_read() 38 val = mt76_rr(dev, MT_EFUSE_DATA(i)); in mt76x02_efuse_read()
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H A D | mt76x02_phy.c | 16 val = mt76_rr(dev, MT_BBP(AGC, 0)); in mt76x02_phy_set_rxpath() 30 val = mt76_rr(dev, MT_BBP(AGC, 0)); in mt76x02_phy_set_rxpath() 176 mt76_rr(dev, MT_RX_STAT_1)); in mt76x02_phy_adjust_vga_gain()
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/freebsd/sys/contrib/dev/mediatek/mt76/mt7996/ |
H A D | debugfs.c | 169 mt76_rr(dev, MT_SWDEF_SER_STATS)); in mt7996_sys_recovery_get() 172 mt76_rr(dev, MT_SWDEF_PLE_STATS)); in mt7996_sys_recovery_get() 175 mt76_rr(dev, MT_SWDEF_PLE1_STATS)); in mt7996_sys_recovery_get() 178 mt76_rr(dev, MT_SWDEF_PLE_AMSDU_STATS)); in mt7996_sys_recovery_get() 181 mt76_rr(dev, MT_SWDEF_PSE_STATS)); in mt7996_sys_recovery_get() 184 mt76_rr(dev, MT_SWDEF_PSE1_STATS)); in mt7996_sys_recovery_get() 187 mt76_rr(dev, MT_SWDEF_LAMC_WISR6_BN0_STATS)); in mt7996_sys_recovery_get() 571 val = mt76_rr(dev, MT_FL_Q_EMPTY); in mt7996_hw_queue_read() 608 val = mt76_rr(dev, MT_PLE_AC_QEMPTY(ac, idx)); in mt7996_sta_hw_queue_read() 661 val = mt76_rr(dev, MT_PLE_FREEPG_CNT); in mt7996_hw_queues_show() [all …]
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H A D | mac.c | 145 msta->airtime_ac[i] = mt76_rr(dev, addr); in mt7996_mac_sta_poll() 206 val = mt76_rr(dev, addr); in mt7996_mac_sta_poll() 209 val = mt76_rr(dev, addr); in mt7996_mac_sta_poll() 225 val = mt76_rr(dev, addr); in mt7996_mac_sta_poll() 1436 mt76_rr(dev, MT_TX_AGG_CNT(band_idx, i)); in mt7996_mac_reset_counters() 1504 val = mt76_rr(dev, reg); in mt7996_phy_get_nf() 2017 cnt = mt76_rr(dev, MT_MIB_RSCR1(band_idx)); in mt7996_mac_update_stats() 2026 cnt = mt76_rr(dev, MT_MIB_SDR6(band_idx)); in mt7996_mac_update_stats() 2029 cnt = mt76_rr(dev, MT_MIB_RVSR0(band_idx)); in mt7996_mac_update_stats() 2038 cnt = mt76_rr(dev, MT_MIB_TSCR0(band_idx)); in mt7996_mac_update_stats() [all …]
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H A D | coredump.c | 106 count = mt76_rr(dev, MT_FW_ASSERT_CNT); in mt7996_coredump_fw_state() 131 dump->pc_stack[0] = mt76_rr(dev, MT_CONN_DBG_CTL_PC_LOG); in mt7996_coredump_fw_stack() 144 mt76_rr(dev, MT_MCU_WM_EXCP_PC_LOG + idx * 4); in mt7996_coredump_fw_stack() 152 mt76_rr(dev, MT_MCU_WM_EXCP_LR_LOG + idx * 4); in mt7996_coredump_fw_stack()
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/freebsd/sys/contrib/dev/mediatek/mt76/mt7603/ |
H A D | eeprom.c | 13 val = mt76_rr(dev, base + MT_EFUSE_CTRL); in mt7603_efuse_read() 25 val = mt76_rr(dev, base + MT_EFUSE_CTRL); in mt7603_efuse_read() 33 val = mt76_rr(dev, base + MT_EFUSE_RDATA(i)); in mt7603_efuse_read() 48 if (mt76_rr(dev, base + MT_EFUSE_BASE_CTRL) & MT_EFUSE_BASE_CTRL_EMPTY) in mt7603_efuse_init() 153 return mt76_rr(dev, MT_EFUSE_BASE + 0x64) & BIT(4); in is_mt7688()
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H A D | soc.c | 34 mdev->rev = (mt76_rr(dev, MT_HW_CHIPID) << 16) | in mt76_wmac_probe() 35 (mt76_rr(dev, MT_HW_REV) & 0xff); in mt76_wmac_probe()
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H A D | pci.c | 43 mdev->rev = (mt76_rr(dev, MT_HW_CHIPID) << 16) | in mt76pci_probe() 44 (mt76_rr(dev, MT_HW_REV) & 0xff); in mt76pci_probe()
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H A D | core.c | 18 intr = mt76_rr(dev, MT_INT_SOURCE_CSR); in mt7603_irq_handler() 29 u32 hwintr = mt76_rr(dev, MT_HW_INT_STATUS(3)); in mt7603_irq_handler()
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H A D | mac.c | 40 mt76_rr(dev, MT_TX_AGG_CNT(i)); in mt7603_mac_reset_counters() 173 u32 val = mt76_rr(dev, addr + 3 * 4); in mt7603_wtbl_set_skip_tx() 344 val = mt76_rr(dev, addr + 2 * 4); in mt7603_wtbl_update_cap() 360 val = mt76_rr(dev, addr + 9 * 4); in mt7603_wtbl_update_cap() 742 u32 w9 = mt76_rr(dev, addr + 9 * 4); in mt7603_wtbl_set_rates() 1514 val = mt76_rr(dev, MT_WPDMA_DEBUG); in mt7603_dma_debug() 1581 val = mt76_rr(dev, addr) >> 16; in mt7603_rx_pse_busy() 1655 u32 val = mt76_rr(dev, MT_AGC(41)); in mt7603_edcca_check() 1778 val = mt76_rr(dev, MT_PHYCTRL_STAT_PD); in mt7603_false_cca_check() 1782 val = mt76_rr(dev, MT_PHYCTRL_STAT_MDRDY); in mt7603_false_cca_check() [all …]
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/freebsd/sys/contrib/dev/mediatek/mt76/mt7615/ |
H A D | mmio.c | 94 intr = mt76_rr(dev, MT_INT_SOURCE_CSR); in mt7615_irq_tasklet() 118 mcu_int = mt76_rr(dev, MT_MCU2HOST_INT_STATUS); in mt7615_irq_tasklet() 122 mcu_int = mt76_rr(dev, MT_MCU_CMD); in mt7615_irq_tasklet() 206 mdev->rev = (mt76_rr(dev, MT_HW_CHIPID) << 16) | in mt7615_mmio_probe() 207 (mt76_rr(dev, MT_HW_REV) & 0xff); in mt7615_mmio_probe()
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H A D | eeprom.c | 18 val = mt76_rr(dev, base + MT_EFUSE_CTRL); in mt7615_efuse_read() 29 val = mt76_rr(dev, base + MT_EFUSE_CTRL); in mt7615_efuse_read() 37 val = mt76_rr(dev, base + MT_EFUSE_RDATA(i)); in mt7615_efuse_read() 53 val = mt76_rr(dev, base + MT_EFUSE_BASE_CTRL); in mt7615_efuse_init() 159 val = mt76_rr(dev, MT_TOP_STRAP_STA); in mt7615_eeprom_parse_hw_cap()
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H A D | mac.c | 124 mt76_rr(dev, MT_MIB_SDR9(0)); in mt7615_mac_reset_counters() 125 mt76_rr(dev, MT_MIB_SDR9(1)); in mt7615_mac_reset_counters() 127 mt76_rr(dev, MT_MIB_SDR36(0)); in mt7615_mac_reset_counters() 128 mt76_rr(dev, MT_MIB_SDR36(1)); in mt7615_mac_reset_counters() 130 mt76_rr(dev, MT_MIB_SDR37(0)); in mt7615_mac_reset_counters() 131 mt76_rr(dev, MT_MIB_SDR37(1)); in mt7615_mac_reset_counters() 1089 val = mt76_rr(dev, addr); in mt7615_mac_get_sta_tid_sn() 1094 val2 = mt76_rr(dev, addr); in mt7615_mac_get_sta_tid_sn() 1233 w0 = mt76_rr(dev, addr); in mt7615_mac_wtbl_update_pk() 1234 w1 = mt76_rr(dev, addr + 4); in mt7615_mac_wtbl_update_pk() [all …]
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H A D | debugfs.c | 23 *val = mt76_rr(dev, dev->mt76.debugfs_reg); in mt7615_reg_get() 286 range = mt76_rr(dev, reg); in mt7615_ampdu_stat_read_phy() 290 range = mt76_rr(dev, reg + 4); in mt7615_ampdu_stat_read_phy() 370 val = mt76_rr(dev, MT_PLE_AC_QEMPTY(acs, wmm_idx)); in mt7615_queues_acq() 461 put_unaligned_le32(mt76_rr(dev, MT_WF_RMAC_MAR0), addr); in mt7615_ext_mac_addr_read() 462 put_unaligned_le16((mt76_rr(dev, MT_WF_RMAC_MAR1) & in mt7615_ext_mac_addr_read()
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